Silicon Carbide Hot-Wall Epitaxy for Large-Area, High-Voltage Devices

2008 ◽  
Vol 1069 ◽  
Author(s):  
Michael O'Loughlin ◽  
K. G. Irvine ◽  
J. J. Sumakeris ◽  
M. H. Armentrout ◽  
B. A. Hull ◽  
...  

ABSTRACTThe growth of thick silicon carbide (SiC) epitaxial layers for large-area, high-power devices is described. Horizontal hot-wall epitaxial reactors with a capacity of three, 3-inch wafers have been employed to grow over 350 epitaxial layers greater than 100 μm thick. Using this style reactor, very good doping and thickness uniformity and run-to-run reproducibility have been demonstrated. Through a combination of reactor design and process optimization we have been able to achieve the routine production of thick epitaxial layers with morphological defect densities of around 1 cm−2. The low defect density epitaxial layers in synergy with improved substrates and SiC device processing have resulted in the production of 10 A, 10 kV junction barrier Schottky (JBS) diodes with good yield (61.3%).

1998 ◽  
Vol 512 ◽  
Author(s):  
S. Rendakova ◽  
N. Kuznetsov ◽  
N. Savkina ◽  
M. Rastegaeva ◽  
A. Andreev ◽  
...  

ABSTRACTThe characteristics of SiC high-power devices are currently limited by the small area of the devices, which is usually less than 1 sq. mm. In order to increase device area, defect density in SiC epitaxial structures must be reduced. In this paper, we describe properties of silicon carbide epitaxial layers grown on 4H-SiC wafers with reduced micropipe density. These layers were grown by the vacuum sublimation method. Large area Schottky barriers (up to 8 mm2) were fabricated on SiC epitaxial layers and characterized.


2006 ◽  
Vol 527-529 ◽  
pp. 1163-1166 ◽  
Author(s):  
Dominique Tournier ◽  
Peter Waind ◽  
Phillippe Godignon ◽  
L. Coulbeck ◽  
José Millan ◽  
...  

Due to the significant achievements in SiC bulk material growth and in SiC device processing technology, this semiconductor has received a great interest for power devices, particularly for SiC high-voltage Schottky barrier rectifiers. The main difference to ultra fast Si pin diodes lies in the absence of reverse recovery charge in SiC SBDs. This paper reports on 4.5kV-8A SiC Schottky diodes / Si-IGBT modules. The Schottky termination design and the fabrication process gives a manufacturing yield of 40% for large area devices on standard starting material. Modules have been successfully assembled, containing Si-IGBTs and 4.5kV-SiC Schottky diodes and characterized in both static and dynamic regimes. The forward dc characteristics of the modules show an on-resistance of 33mohm.cm2 @ room temperatue (RT) and a very low reverse leakage current density (JR < 10 5A/cm2 @ 3.5kV). An experimental breakdown voltage higher than 4.7kV has been measured in the air on polyimide passivated devices. This value corresponds to a junction termination efficiency of at least 80% according to the epitaxial properties. These SiC SBDs are well suited for high voltage, medium current, high frequency switching aerospace applications, matching perfectly as freewheeling diodes with Si IGBTs.


1999 ◽  
Vol 572 ◽  
Author(s):  
Erwin Schmitt ◽  
Robert Eckstein ◽  
Martin Kölbl ◽  
Amd-Dietrich Weber

ABSTRACTFor the growth of 2″ 6H-SiC a sublimation growth process was developed. By different means of characterization crystal quality was evaluated. Higher defect densities, mainly in the periphery of the crystals were found to be correlated to unfavourable process conditions. Improvement of thermal boundary conditions lead to a decreased defect density and better homogeneity over the wafer area.


2012 ◽  
Vol 717-720 ◽  
pp. 137-140 ◽  
Author(s):  
Jie Zhang ◽  
Gil Yong Chung ◽  
Edward K. Sanchez ◽  
Mark J. Loboda ◽  
Siddarth G. Sundaresan ◽  
...  

This paper reports the progress of the thick epitaxy development at Dow Corning. Epiwafers with thickness of 50 – 100 m have been grown on 4° off-axis 76mm 4H SiC substrates. Smooth surface with RMS roughness below 1nm and defect density down to 2 cm-2 are achieved for 80 - 100 m thick epiwafers. Long carrier lifetime of 2 – 4 s are routinely obtained, and low BPD density in the range of 50 down to below 10 cm-2 is confirmed. High voltage JBS diodes have been successfully fabricated on these wafers with thick epitaxial layers.


2020 ◽  
Vol 25 (6) ◽  
pp. 483-396
Author(s):  
A.V. Afanasev ◽  
◽  
V.A. Ilyin ◽  
V.V. Luchinin ◽  
S.A. Reshanov ◽  
...  

Currently, chemical gas deposition is the main method for producing high-quality and reproducible epitaxial layers for commercial silicon carbide (SiC) power devices. Based on the experience of ETU «LETI» in the synthesis of monocrystalline SiC, an analysis of the current state of silicon carbide gas phase epitaxy (CVD) technology was carried out. It has been shown that modern CVD reactors allow to implement the growth processes of SiC epitaxial structures of high quality with the following parameters: substrates diameter up to 200 mm; thicknesses of epitaxial layers from 0.1 to 250 μm; layers of n - and p -types conductivity with ranges of doping levels 10-10 cm and 10-10 cm, respectively. At the same time, setting up the technology of the reproducible high-quality growth of epitaxial layers is an individual task for a specific type of reactor. It requires a detailed consideration of the technological factors presented in this paper, which at the end determine the achievable parameters of SiC-epitaxial products


2014 ◽  
Vol 778-780 ◽  
pp. 750-753 ◽  
Author(s):  
Yuu Okada ◽  
Hiroaki Nishikawa ◽  
Yasuhisa Sano ◽  
Kazuya Yamamura ◽  
Kazuto Yamauchi

In recent years, silicon (Si) has been mainly used in power devices, but the limit of its performance is being reached. Therefore, silicon carbide (SiC) power devices have been attracting attention because they enable the fabrication of devices with low power consumption. To reduce the on-resistance in vertical power transistors, backside thinning is required after device processing. However, it is difficult to thin a SiC wafer with a high removal rate by conventional mechanical processing because its high hardness and brittleness cause cracking and chipping during thinning. Therefore, we have attempted to thin a SiC wafer using plasma chemical vaporization machining (PCVM), which is plasma etching using atmospheric-pressure plasma. In this study, we describe a machining property using a newly developed slit electrode that is composed of two parts and has a slit that allows for a new gas to pass.


2007 ◽  
Vol 556-557 ◽  
pp. 77-80 ◽  
Author(s):  
Joseph J. Sumakeris ◽  
Brett A. Hull ◽  
Michael J. O'Loughlin ◽  
Marek Skowronski ◽  
Vijay Balakrishna

We detail a comprehensive approach to preparing epiwafers for bipolar SiC power devices which entails etching the substrate, growing a semi-sacrificial basal plane dislocation (BPD) conversion epilayer, polishing away a portion of that conversion epilayer to recover a smooth surface and then growing the device epilayers following specific methods to prevent the reintroduction of BPDs. With our best processing, we achieve a BPD density of < 10 cm-2 and an extended defect density of < 1.5 cm-2. Specifics of low BPD processing and particular concerns and metrics will be discussed in regard to process optimization and simplification.


MRS Bulletin ◽  
2005 ◽  
Vol 30 (4) ◽  
pp. 299-304 ◽  
Author(s):  
T. Paul Chow

AbstractThe successful commercialization of unipolar Schottky rectifiers in the 4H polytype of silicon carbide has resulted in a market demand for SiC high-power switching devices. This article reviews recent progress in the development of high-voltage 4H-SiC bipolar power electronics devices.We also present the outstanding material and processing challenges, reliability concerns, and future trends in device commercialization.


2013 ◽  
Vol 740-742 ◽  
pp. 809-812 ◽  
Author(s):  
Hossein Elahipanah ◽  
Arash Salemi ◽  
Benedetto Buono ◽  
Carl Mikael Zetterling ◽  
Mikael Östling

Silicon carbide (SiC) is one of the most attractive semiconductors for high voltage applications. The breakdown voltage of SiC-based devices highly depends on the variation of the fabrication process including doping of the epilayers and the etching steps. In this paper, we show a way to diminish this variability by employing novel trench structures. The influence of the process variations in terms of doping concentration and etching has been studied and compared with conventional devices. The breakdown voltage variation (ΔVBR) of 450 V and 2100 V is obtained for the ±20% variation of doping concentration of the devices with and without the trench structures, respectively. For ±20% variation in etching steps, the maximum ΔVBR of 380 V is obtained for the device with trench structures in comparison to 1800 V for the conventional structure without trench structures. These results show that the breakdown voltage variation is significantly reduced by utilizing the proposed structure.


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