3D Process Integration – Requirements and Challenges

2008 ◽  
Vol 1112 ◽  
Author(s):  
Juergen Max Wolf ◽  
Armin Klumpp ◽  
Kai Zoschke ◽  
Robert Wieland ◽  
Lars Nebrich ◽  
...  
Keyword(s):  
System Integration ◽  
New Technologies ◽  
Process Integration ◽  
High Volume ◽  
System Level ◽  
Wafer Level ◽  
System Architectures ◽  
Future System ◽  
3D Packaging ◽  
Third Dimension

AbstractHeterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.

Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001555-001595
Author(s):  
Cornelia Tsang ◽  
Janet Okada ◽  
Eric Huenger
Keyword(s):  
Printed Circuit Boards ◽  
Process Integration ◽  
Product Yield ◽  
Wafer Surface ◽  
Wafer Level ◽  
Design Elements ◽  
Conformal Coating ◽  
3D Packaging ◽  
Study Process ◽  
Negative Tone

As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used in MEMs, printed circuit boards, backside vias, etc, and can play a significant role in enabling new 3D packaging solutions. In this research, the successful fabrication of an Optochip silicon interposer, which integrates electrical and optical components onto a single substrate with high density interconnection, was enabled through use of electrodeposited (ED) photoresist. The Optochip interposer was manufactured in a standard 200 mm semiconductor fab and this precipitated the process integration requirement of first etching “optical vias” into the silicon at wafer-level prior to the final lithography steps. As such, challenging topography was introduced into the system. A resist solution able to address the following conditions was required: 1) sufficient conformal coating into large optical vias measuring 150 um diameter by 200 um depth, 2) no resist pull-back over sharp 90 degree angle corners where the optical vias met the wafer surface, 3) ability to resolve 30 um diameter surface pads at 50 um pitch and 4) chemical resistance to Ni and cyanide-based Au plating baths. This presentation will discuss how various photoresists were examined that resulted in ED photoresist being chosen for the aforementioned application. Both negative-tone and positive-tone ED photoresists were considered. Experiments to study process parameters and environmental factors on product yield were performed using test wafers with optical vias. These experiments resulted in positive-tone ED photoresist being selected. Test wafers plated with NiAu resulted in ~ 90% process yield. The presentation will conclude by demonstrating the ability to achieve good yield on integrated product wafers.

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

2013 ◽  
Vol 2013 (1) ◽  
pp. 000447-000451 ◽  
Author(s):  
Michael Vincent ◽  
Doug Mitchell ◽  
Jason Wright ◽  
Yap Weng Foong ◽  
Alan Magnus ◽  
...  
Keyword(s):  
System Integration ◽  
System Performance ◽  
Electrical Characterization ◽  
Emerging Technology ◽  
Volumetric Efficiency ◽  
Wafer Level ◽  
Novel Technologies ◽  
3D Packaging ◽  
Packaging Space ◽  
On Chip

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

Packaging without the Package - A More Holistic Moore's Law

2017 ◽  
Vol 2017 (S1) ◽  
pp. 1-40
Author(s):  
Subramanian S. Iyer (Subu)
Keyword(s):  
System Integration ◽  
System Level ◽  
Heterogeneous Integration ◽  
Power Performance ◽  
Wafer Level ◽  
Innovative Materials ◽  
Barrier To Entry ◽  
On Chip ◽  
Market Consolidation ◽  
Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

Packaging and Integration Strategy for mm-Wave Products

2018 ◽  
Vol 2018 (1) ◽  
pp. 000252-000258 ◽  
Author(s):  
Urmi Ray ◽  
NJ Cho ◽  
YC Kim ◽  
SW Yoon ◽  
WK Choi ◽  
...  
Keyword(s):  
Form Factor ◽  
Antenna Arrays ◽  
System Integration ◽  
High Performance ◽  
Heat Dissipation ◽  
System Level ◽  
Wafer Level ◽  
Automotive Radar ◽  
Rf Transceiver ◽  
Trade Offs

Abstract This paper is a follow on to the paper presented at the IMAPS 14th International Conference DEVICE PACKAGING and will provide more comprehensive case studies of few different system integration strategies for high frequency packaging. The packaging options vary widely based on the end market requirements, from performance, thermal, types and numbers of antenna arrays as well as the RF transceiver ICs. Tied closely to these performance related requirements is competing trade-offs of reliability, form factor and cost. We present assessment of packaging structures for (a) high performance mm-Wave network product and (b) consumer/mobile product and (c) automotive radar product. The former (a) is generally not challenged by form factor and can be enhanced by the addition of more antenna arrays and RFICs. However, care has to be taken to address the thermal solutions for effective heat dissipation as well as manufacturability issues as the package size may target ~400mm2 for Gen 1 and double or triple the area for subsequent generations. For (b), the primary drivers are cost and form factor. To manage antenna propagation and losses in a constrained form factor, mobile products generally require antenna in package (AiP) integration. The integration of the antenna within the same package as the RF IC greatly reduces the difficulty at the system level. This approach coupled to aggressive miniaturization of the antenna itself, using the same substrate technologies as the SiP leads to a new class of sub-systems termed Antenna in Package (AiP). This is extremely challenging from design, manufacturability and test perspectives. For example, Fan out wafer level packaging, such as eWLB packaging provides extremely smooth copper surfaces with tight etch tolerance compared to standard laminate based packaging. However, having multiport antenna structures fabricated in fan out technology with inductance matching and efficient ground ports, continue to be problematic. Hence adoption of 3D structures, in conjunction with SIP integration (with inductors and IPDs) can potentially provide relief. Inductors can also be built into the eWLB structure using the RDL as well as in the laminate packages using substrate embedded thin film cores.

Embedded solutions: Fan-out and Embedded Die Packages market and technology trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000235-000238
Author(s):  
Jérôme Azémar
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
Low Cost ◽  
High Volume ◽  
Added Value ◽  
System Level ◽  
Wafer Level ◽  
High Expectations ◽  
Interesting Approach ◽  
Pcb Manufacturing

Embedded packages are nowadays not anymore just an interesting approach for some specific application. Benefiting from 3D TSV high cost, and consequently delays, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players. In this presentation we will focus on two main types of embedded packages, those that are most of interest at the moment: Fan-Out and Embedded Dies packages. The principle of Fan Out technology is to embed products in a molded compound and allow redistribution layers pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and Stats ChipPAC using eWLB type of Fan-Out. Market for Fan-Out packages in 2014 almost reached $200M and a 20% growth for the coming years is expected. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like SPIL or J-Devices are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The principle of Embedded die packages has the same purpose of promoting high integration due to placing chips within the substrate but with a different approach: Embedding is done in laminate substrates. This process is pushed by PCB manufacturers such as AT&S and could create a new supply chain with new players. One of the main advantages is to use a mature and cheap manufacturing chain created for PCB manufacturing and then having low cost for a technology that would allow a good integration and access to both sides of the chips easily. On the other hand, Embedded Die technologies are still waiting for a high volume project that shall be coming once higher yield, better resolution and clarification of the supply chain will be achieved. In this presentation we will describe what the strategies to reach that goal are. Both technologies seem to be competing but are actually complementary and often targeting different markets. Key customers already qualified them and will open the gates for the fast growing packaging market. The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out and embedded die packaging approaches by applications, business models and major players will be reviewed.

scholarly journals Jurisdictional Coordination of Integrated HIV Prevention and Patient Care Planning and Implementation

2019 ◽  
Vol 18 ◽  
pp. 232595821988053
Author(s):  
Graham Fitzgerald Watts ◽  
Deidre Kelley ◽  
Matthew Maximillion Wilson ◽  
Sandy Arts ◽  
Joseph Mims
Keyword(s):  
Hiv Prevention ◽  
System Integration ◽  
Service Providers ◽  
Service System ◽  
Community Based Participatory Research ◽  
System Level ◽  
Local Response ◽  
Community Based ◽  
Future System ◽  
System Improvement

Jacksonville, Florida, provides services to persons living with the HIV. A federal call for integrated HIV prevention and treatment was published on June 19, 2015. This study unveils the principles that guided the local response to that call. Service providers have not systematically engaged in strategic planning for system improvement, the absence of which defines the boundaries and properties of the service system. Integration requires a unifying strategy as it draws leaders from their respective silos. Directed leadership, community-based participatory research, and action research provided a science-based framework for integration. Quantitatively, one-third of the planning implementation journey has elapsed, and 46% of the 75 planned activities have either reached fulfillment or are ongoing. Another one-fourth is in progress and slightly more than one-fourth (28%) are pending. Qualitatively, this study recorded 7 system-level changes. Progress to date is a harbinger of future system-level changes.

Embedded solutions: Fan-out and Embedded Dies Packages market and technology trends

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000182-000216 ◽  
Author(s):  
Jerome AZEMAR ◽  
Rozalia BEICA ◽  
Thibault BUISSON ◽  
Andrej IVANCOVIC ◽  
Amandine PIZZAGALLI
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
Low Cost ◽  
High Volume ◽  
Added Value ◽  
System Level ◽  
Wafer Level ◽  
High Expectations ◽  
Interesting Approach ◽  
Pcb Manufacturing

Embedded packages are nowadays not anymore just an interesting approach for some specific application. Benefiting from 3D TSV high cost, and consequently delays, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players. In this presentation we will focus on two main types of embedded packages, those that are most of interest at the moment: Fan-Out and Embedded Dies packages. The principle of Fan Out technology is to embed products in a molded compound and allow redistribution layers pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and Stats ChipPAC using eWLB type of Fan-Out. Market for Fan-Out packages in 2014 almost reached $200M and a 20% growth for the coming years is expected. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like SPIL or J-Devices are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The principle of Embedded dies package has the same purpose of promoting high integration due to placing chips within the substrate but with a different approach: Embedding is done in laminate substrates. This process is pushed by PCB manufacturers such as AT&S and could create a new supply chain with new players. One of the main advantages is to use a mature and cheap manufacturing chain created for PCB manufacturing and then having low cost for a technology that would allow a good integration and access to both sides of the chips easily. On the other hand, Embedded Die technologies are still waiting for a high volume project that shall be coming once higher yield, better resolution and clarification of the supply chain will be achieved. In this presentation we will describe what the strategies to reach that goal are. Both technologies seem to be competing but are actually complementary and often targeting different markets. Key customers already qualified them and will open the gates for the fast growing packaging market. The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out and embedded die packaging approaches by applications, business models and major players will be reviewed.

Integration of MEMS in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-23 ◽  
Author(s):  
Steffen Kroehnert ◽  
André Cardoso ◽  
Steffen Kroehnert ◽  
Raquel Pinto ◽  
Elisabete Fernandes ◽  
...  
Keyword(s):  
System Integration ◽  
Low Cost ◽  
High Volume ◽  
Building Blocks ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Mems Sensors ◽  
Packaging Technology ◽  
Wafer Level Packaging ◽  
Dense System

The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/Intel's eWLB technology, aiming to overcome the current limits for MEMS/Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.

Fan-Out Wafer-Level-Packaging: Market and Technology Trends

2016 ◽  
Vol 2016 (1) ◽  
pp. 000176-000179 ◽  
Author(s):  
Jérôme Azémar
Keyword(s):  
Cost Reduction ◽  
Flip Chip ◽  
Business Models ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
High Volume ◽  
Added Value ◽  
System Level ◽  
Wafer Level ◽  
High Expectations

Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D/3D IC solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. Embedded packages are nowadays not anymore just an interesting approach for specific applications. Benefiting from 3D TSV high cost, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players, lately most notably TSMC. In this work we will focus on one main type of embedded package of most interest at the moment: Fan-Out wafer level package. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, with many other developments from OSATs and an aggressive technology from TSMC (inFO). The market for Fan-Out packages in 2015 almost reached $500M, with potential breakthrough events in store in 2016 that could triple the 2015 market and continue further with more than 30% growth. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

High-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC

2011 ◽  
Vol 2011 (1) ◽  
pp. 000820-000827
Author(s):  
Atsuko IIDA ◽  
Yutaka ONOZUKA ◽  
Hiroshi YAMADA ◽  
Toshihiko NAGANO ◽  
Kazuhiko ITAYA
Keyword(s):  
Low Temperature ◽  
System Integration ◽  
Fem Simulation ◽  
High Sensitivity ◽  
High Accuracy ◽  
System Level ◽  
Level System ◽  
Wafer Level ◽  
High Quality ◽  
On Chip

This paper reports an advanced process to realize high-quality multiple global layers on high-accuracy chip-redistributed wafer for wafer-level system integration using pseudo-SOC. We have been developing pseudo-SOC (p-SOC) technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. The basic process has been established for p-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of p-SOC technology was based on a single global layer consisting of an insulating layer and a conductive layer, which limited the range of application. It is desirable to realize high-quality multiple global layers on the high-accuracy chip-redistributed wafer in order to expand its application toward system-level integration. For this purpose, it is necessary to keep all processes at low temperature for the reduction of warpage in the resin-based chip-redistributed wafer during several resin curing processes, to readjust resin-based materials, and to obtain high accuracy of chip position in chip-redistributed wafer. We developed the advanced p-SOC process to resolve these technical issues by improving the hardening process of resin, employing low-temperature-curing polyimide and optimizing the stress analysis by FEM simulation. As a result, realization of a novel one-chip module for a versatile high-sensitivity amplifier is demonstrated.

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