Viscoelastic Stress Relief in Patterned Silicon-on-Insulator Structures

1988 ◽  
Vol 130 ◽  
Author(s):  
Theodore J. Letavic ◽  
Edward W. Maby ◽  
Ronald J. Gutmann
Keyword(s):  
Mechanical Model ◽  
Silicon Film ◽  
Stress Relief ◽  
Silicon On Insulator ◽  
Viscoelastic Flow ◽  
Glass Layer ◽  
Flow Mechanism ◽  
Pattern Size ◽  
Phosphosilicate Glass ◽  
Zone Melt

AbstractA high-temperature viscoelastic stress relief technique has been investigated as a means for reducing in-plane stress encountered during zone-melt recrystallization of patterned silicon-on-insulator structures. This technique incorporates a phosphosilicate glass layer between the silicon film and the insulating substrate to provide a viscous flow mechanism for stress relief within the composite structure. The stress relaxation can bequalitatively described by a mechanical model which couples thermal expansion and viscoelastic flow. The model predicts the time constant for stress relief at high temperatures as a function of pattern size, and the results are useful as a design aid for zone-melt recrystallization experiments.

Elimination of Defects in Laser-Recrystallized SOI by Stress Relief

1987 ◽  
Vol 107 ◽  
Author(s):  
Andre Martinez ◽  
Ranjana Pandya ◽  
Emil Arnold
Keyword(s):  
Subgrain Boundary ◽  
Silicon Film ◽  
Large Degree ◽  
Stress Relief ◽  
Silicon On Insulator ◽  
Boundary Density ◽  
Density Of Dislocations ◽  
Low Viscosity ◽  
Degree Of Control ◽  
Zone Melt

AbstractWe report the application of a stress-relief technique aimed at reducing the density of dislocations and subgrain boundaries in laser-recrystallized Silicon-On-Insulator (SOI) material. By providing alternate mechanisms for relieving the stresses responsible for defect generation in the Si film, it is possible to exercise a large degree of control over the subgrain boundary density. Large areas of SOI material completely free of dislocations and subgrain boundaries have been obtained by inserting a low-viscosity layer under the silicon film and using an appropriately shaped cw laser beam as the heat source. During the process of zone-melt recrystallization this layer softens and provides an alternative stress relief mechanism, thus reducing the mechanical constraint on the growing crystal. Several examples of subgrain boundary control are described, which have resulted in crystalline regions in excess of 300 μm by several millimeters completely free of low-angle grain boundaries and dislocations.

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  
Keyword(s):  
Structural Properties ◽  
Solid Phase ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Defect Band ◽  
Future Technology ◽  
Ultrashallow Junctions ◽  
P Type ◽  
Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Transfer of an ultrathin single crystal silicon film from a Silicon On Insulator to a polymer

2020 ◽  
pp. 100107
Author(s):  
L.G. Michaud ◽  
E. Azrak ◽  
C. Castan ◽  
F. Fournel ◽  
F. Rieutord ◽  
...  
Keyword(s):  
Single Crystal ◽  
Silicon Film ◽  
Single Crystal Silicon ◽  
Silicon On Insulator ◽  
Crystal Silicon

Non-Destructive Assessment of Thin Film Stresses and Crystal Qualify of Silicon on Insulator Materials with Raman Spectroscopy

1990 ◽  
Vol 188 ◽  
Author(s):  
Ingrid De Wolf ◽  
Jan Vanhellemont ◽  
Herman E. Maes
Keyword(s):  
Thin Film ◽  
Electron Microscopy ◽  
Raman Spectroscopy ◽  
Cross Section ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Micro Raman Spectroscopy ◽  
Transmission Electron ◽  
Non Destructive ◽  
Zone Melt

ABSTRACTMicro Raman spectroscopy (RS) is used to study the crystalline quality and the stresses in the thin superficial silicon layer of Silicon-On-Insulator (SO) materials. Results are presented for SIMOX (Separation by IMplanted OXygen) and ZMR (Zone Melt Recrystallized) substrates. Both as implanted and annealed SIMOX structures are investigated. The results from the as implanted structures are correlated with spectroscopic ellipsometry (SE) and cross-section transmission electron microscopy (TEM) analyses on the same material. Residual stress in ZMR substrates is studied in low- and high temperature gradient regions.

Stress relief pattern in an evaporated silicon film

1973 ◽  
Vol 15 (3) ◽  
pp. S37-S40
Author(s):  
W.D. Edwards
Keyword(s):  
Silicon Film ◽  
Stress Relief

Modeling and Designing a Device Using MuGFETs

2008 ◽  
Author(s):  
V. K. Lamba ◽  
Derick Engles ◽  
S. S. Malik
Keyword(s):  
Gate Dielectric ◽  
Silicon Film ◽  
General Rule ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Radius Of Curvature ◽  
Short Channel ◽  
Dielectric Thickness ◽  
Fin Thickness

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

The Physical and Electrical Properties of Buried Nitride Soi Structures Synthesized By Nitrogen Ion Implantation

1985 ◽  
Vol 53 ◽  
Author(s):  
C. Slawinski ◽  
B.-Y. Mao ◽  
P.-H. Chang ◽  
H.W. Lam ◽  
J.A. Keenan
Keyword(s):  
Ion Implantation ◽  
Nitrogen Concentration ◽  
Silicon Film ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Crystal Silicon ◽  
Nitrogen Ion Implantation ◽  
Donor Formation ◽  
Nitrogen Ion

ABSTRACTBuried nitride silicon-on-insulator (SOI) structures have been fabricated using the technique of nitrogen ion implantation. The crystallinity of the top silicon film was found to be exceptionally good. The minimum channeling yield, Xmin' was better than 3%. This is comparable to the value observed for single crystal silicon. The buried insulator formed during the anneals has been identified as polycrystalline α-Si3 N4 with numerous silicon inclusions. This nitride, however, has been found to remain amorphous in regions at the center of the implant where the nitrogen concentration exceeds the stoichiometric level of Si3N4. Nitrogen donor formation in the top silicon layer has also been observed.

Reduction of Thermal Stress in Mbe Grown GaAs/Si by Patterning

1989 ◽  
Vol 145 ◽  
Author(s):  
J. P. Van Der Ziel ◽  
Naresh Chand ◽  
J. S. Weiner
Keyword(s):  
Thermal Stress ◽  
Tensile Stress ◽  
Layer Thickness ◽  
No Reduction ◽  
Stress Relief ◽  
Patterned Growth ◽  
A Value ◽  
Pattern Size ◽  
Biaxial Tensile Stress ◽  
Weakly Dependent

AbstractThe biaxial tensile stress of 2.65 kbar in as-grown GaAs/Si for T < 100K is reduced by post-growth patterning of the GaAs and the reduction in stress, as determined by photoluminescence and cathodoluminescence, is dependent on the pattern size and shape. For stripe patterns less than 15 gm wide the stress is largely uniaxial with stress relief normal to the stripe direction. Rectangular patterns exhibited stress relief in orthogonal directions, and a 9 x 12 µm2 rectangle exhibited an average stress of 0.5 kbar. For as-grown GaAs/Si layers 0.9 to 3.25 µm thick, the stress is weakly dependent on layer thickness. For T > looK the stress in as-grown GaAs/Si is reduced and at 295K a value of 1.51 ± 0.21 kbar is obtained. With patterned growth, using a native SiO2 mask, no reduction in stress was observed irrespective of the pattern size, indicating the importance of free GaAs edges in obtaining stress relief.

Stress and Microstructure in Phosphorus Doped Polycrystalline Silicon

1992 ◽  
Vol 276 ◽  
Author(s):  
P. Krulevitch ◽  
G. C. Johnson ◽  
R. T. Howe
Keyword(s):  
Film Thickness ◽  
Polycrystalline Silicon ◽  
Stress Gradient ◽  
Stress Relief ◽  
Phosphorus Doping ◽  
Cross Sectional ◽  
Uniform Microstructure ◽  
Phosphosilicate Glass ◽  
Polycrystalline Silicon Films ◽  
Phosphorus Doped

ABSTRACTThe research presented here is an investigation of the effects of phosphorus doping on residual stresses and microstructure in polycrystalline silicon. Undoped polycrystalline silicon films were deposited on phosphosilicate glass layers and annealed at 1050 °C for 5 to 60 minutes. The stress gradient through the film thickness was measured from wafer curvature, and microstructure was examined with cross-sectional TEM. A 20 minute anneal is sufficient for stress relief in initially tensile films and produces a uniform microstructure consisting of 0.1-0.2 µm equi-axed grains.

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