Limiting Native Oxide Regrowth for High-k Gate Dielectrics

2003 ◽  
Vol 765 ◽  
Author(s):  
K. Choi ◽  
H. Harris ◽  
S. Gangopadhyay ◽  
H. Temkin
Keyword(s):  
Silicon Oxide ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Hafnium Dioxide ◽  
Electron Beam Evaporation ◽  
Native Oxide ◽  
Device Applications ◽  
The Difference ◽  
Cleaning Methods

AbstractA cleaning process resulting in atomically smooth, hydrogen-terminated, silicon surface that would inhibit formation of native silicon oxide is needed for high-k gate dielectric deposition. Various cleaning methods thus need to be tested in terms of resistance to native oxide formation. Native oxide re-growth is studied as a function of exposure time to atmospheric ambient using ellipsometry. Hafnium dioxide film (k ~23) is deposited on the as-cleaned substrates by electron beam evaporation and subsequently annealed in hydrogen. The difference in the effective oxide thickness re-grown on surfaces treated with the conventional RCA and modified Shiraki cleaning methods, after one-hour exposure, can be as large as 2 Å. This is significant in device applications demanding equivalent oxide thickness less than 20 Å. The degree of hydrogen passivation, surface micro-roughness and organic removal capability are considered to be the main factors that explain the differences between the cleaning methods. Data derived from capacitance-voltage analysis of test capacitors verified the trend observed in the native oxide thickness measurements. An increase of 10~15 % in accumulation capacitance is observed in the samples treated by the new cleaning method.

Electrical Characteristics of TaOxNy/ZrSixOy Stack Gate Dielectric for MOS Device Applications

2001 ◽  
Vol 670 ◽  
Author(s):  
Hyungsuk Jung ◽  
Hyundoek Yang ◽  
Kiju Im ◽  
Hyunsang Hwang
Keyword(s):  
Interfacial Layer ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Tem Analysis ◽  
Mos Capacitors ◽  
Zirconium Silicate ◽  
Transmission Electron ◽  
High K ◽  
Device Applications

ABSTRACTThis letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

scholarly journals Electrical and Optical Characteristics of SSI-LED Made from Capacitor Containing Tri-Layer WOx Embedded Zr-Doped HfOx Gate Dielectric

2021 ◽  
Author(s):  
Wen-Shan Lin ◽  
Yue Kuo
Keyword(s):  
Dielectric Layer ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Optical Characteristics ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
Light Emitting ◽  
Light Emitting Devices ◽  
Warm White Light ◽  
The Difference

Abstract Solid-state incandescent light emitting devices made from MOS capacitors with the WOx embedded Zr-doped HfOx gate dielectric were characterized for electrical and optical characteristics. Devices made from capacitors containing Zr-doped HfOx and WOx, gate dielectrics were also fabricated for comparison. The device with the WOx embedded gate dielectric layer had electrical and light emitting characteristics between that with WOx gate dielectric layer and that with the Zr-doped HfOx but no WOx embedded gate dielectric layer. The difference can be explained by the nano-resistor formation process and the content of the high emissivity W in the nano-resistor. The device made from the WOx embedded Zr-doped HfOx gate dielectric MOS capacitor is applicable to areas where uniform emission of warm white light is required.

The Effect of Amorphous Silicon Layer in PE-CVD Titanium Polycide Gate Dielectrics

1990 ◽  
Vol 182 ◽  
Author(s):  
Shih-Chang Chen ◽  
Akihiro Sakamoto ◽  
Hiroyuki Tamura ◽  
Masaki Yoshimaru ◽  
Masayoshi Ino
Keyword(s):  
Amorphous Silicon ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Film Surface ◽  
Silicon Layer ◽  
Film Deposition ◽  
Titanium Silicide ◽  
Native Oxide ◽  
Chemical Vapor Deposition Method ◽  
Dielectric Degradation

AbstractTitanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a—Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE—CVD). The effect of a—Si layer in PE—CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a—Si layer effect, three types of samples were prepared on gate SiO2 film with following structures: a) a—Si / TiSil.1 / a—Si / phosphorus (P) doped poly—Si, b) a—Si / TiSi1.1 / non—doped poly—Si / P doped poly—Si and c) a—Si / TiSi1.1 / P doped poly—Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre—cleaning treatment was performed in—situ on the poly—Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE—CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a—Si film as the under layer in decreasing the gate dielectric degradation. This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly—Si films, whichrestrains the TiSix local penetration.

Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

2003 ◽  
Vol 765 ◽  
Author(s):  
Daewon Ha ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deposition Rate ◽  
Silicon Germanium ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Gate Leakage ◽  
Process Technology ◽  
Cmos Scaling

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

The Effect of Amorphous Silicon Layer in Pe-Cvd Titanium Polycide Gate Dielectrics

1990 ◽  
Vol 181 ◽  
Author(s):  
Shih-Chang Chen ◽  
Akihiro Sakamoto ◽  
Hiroyuki Tamura ◽  
Masaki Yoshimaru ◽  
Masayoshi Ino
Keyword(s):  
Amorphous Silicon ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Film Surface ◽  
Silicon Layer ◽  
Film Deposition ◽  
Titanium Silicide ◽  
Native Oxide ◽  
Chemical Vapor Deposition Method ◽  
Dielectric Degradation

ABSTRACTTitanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a-Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE-CVD). The effect of a-Si layer in PE-CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a-Si layer effect, three types of samples were prepared on gate SiO2 film with following structures : a) a-Si / TiSi-1.1 / a-Si / phosphorus (P) doped poly-Si, b) a-Si / TiSi-1.1 / non-doped poly-Si / P doped poly-Si and c) a-Si / TiSi1.1 / P doped poly-Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre-cleaning treatment was performed in-situ on the poly-Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE-CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a-Si film as the under layer in decreasing the gate dielectric degradation . This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly-Si films, which restrains the TiSix local penetration.

Ultra-Thin Zirconium Silicate Filmsc With Good Physical And Electrical Properties For Gate Dielectric Applications

2000 ◽  
Vol 648 ◽  
Author(s):  
Easwar Dharmarajan ◽  
Wen-Jie Qi ◽  
Renee Nieh ◽  
Laegu Kang ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Interface Quality ◽  
Good Thermal Stability ◽  
Cmos Scaling ◽  
Zirconium Silicate

AbstractThe need for alternative gate dielectrics to replace conventional SiO2 is increasing to facilitate further CMOS scaling. One of the most promising materials for use as an alternative gate dielectric is Zr silicate due to its thermodynamic stability on Si and its good interface quality with Si. In this study, ultra-thin Zr silicate films (45 – 60 Å thick) with different Zr compositions have been deposited on Si using magnetron reactive co-sputtering. The Zr composition was kept below the stoichiometric value of about 16% to prevent precipitation of ZrO2and to have Si rich films for better interface quality. Films were rapid thermal annealed in N2 ambient up to 9000C and Pt was used as the gate electrode. Electrical characterization of these films was done using HP 4156 and HP 4194 parameter analyzers. Based on these studies, we demonstrate Zr silicate films with equivalent oxide thickness (EOT) of less than 14 Å with gate leakage significantly lower thanSiO2 of similar thickness and hysteresis of < 20mV ( in a sweep from –3 to 3 V). The films exhibit good thermal stability on Si even after 900 0C annealing as shown by a minimal increase in EOT with annealing. TEM and XPS analyses show high quality Zr silicate films that remain stable and amorphous even at 900 0C.

Fabrication of Organic Thin Film Transistors Using Low Temperature, Soluble Silicon Oxide as the Gate Dielectrics

2006 ◽  
Vol 965 ◽  
Author(s):  
Jeng-Hua Wei ◽  
HorngJiunn Lin ◽  
Ying-Ren Chen
Keyword(s):  
Thin Film ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Gate Insulator ◽  
Breakdown Field ◽  
Organic Thin Film ◽  
Water Based ◽  
Low Threshold

ABSTRACTIn this paper, a unique water-based, liquid phase deposited silicon oxide (LPD SiO2) is adapted to the fabrication process of the organic thin film transistor (OTFT). Through the use of this process, an OTFT with a silicon oxide gate insulator is successfully fabricated at 100°C or less. At this low process temperature, the SiO2 functions efficiently as a gate dielectric with the breakdown field being larger than 5 MV/cm, the leakage current being near 1 pA/um2 with a gate bias of 20 V and the surface roughness being less than 1nm. Due to the high quality silicon oxide, the oxide-gated OTFT shows the low threshold voltage (-1 ∼ -2V) and medium on/off current ratio (∼1000). Because this oxide is a water-based process, it is highly resistant to the following soluble semiconductor material and its solvent.

Single Wafer CVD of Silicon Nitride for Cmos Gate Applications

1999 ◽  
Vol 567 ◽  
Author(s):  
C. Pomarede ◽  
C. Werkhoven ◽  
J. Weidmann ◽  
T. Bergman ◽  
A. Gschwandtner ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Silicon Nitride Films ◽  
Excellent Growth ◽  
Gate Dielectric Material ◽  
Cluster Tool

ABSTRACTThe MESC/CTMC compatible, Advance 2500 cluster tool made by ASM is evaluated for the manufacturing of CMOS gate stack structures based on CVD silicon nitride rather than thermally grown silicon oxide as the gate dielectric material, and polysilicon as the gate electrode material. With two different CVD chemistries excellent growth characteristics and thickness uniformity control of the silicon nitride is demonstrated. Electrical assessment reveals lower leakage current as compared to silicon oxide and minimal hysteresis in C-V curves, even for gates stacks that have an equivalent oxide thickness below 1.5nm. The best properties are for silicon nitride films that also have a low H2 content.

Wafer Cleaning Influence on the Roughness of the Si/SiO2 Interface

1995 ◽  
Vol 386 ◽  
Author(s):  
A. Munkholm ◽  
S. Brennan ◽  
Jon P. Goodbread
Keyword(s):  
Integrated Circuits ◽  
Semiconductor Industry ◽  
Native Oxide ◽  
X Ray Scattering ◽  
Wafer Cleaning ◽  
Thermal Oxide ◽  
Before And After ◽  
The Difference ◽  
Cleaning Methods

ABSTRACTThe roughness of the Si/SiO2 interface has a great impact on the electrical properties of the gate-oxide in integrated circuits and consequently it is a large concern for the semiconductor industry. As the thickness of the oxide is decreased, the role of the roughness becomes more critical for the device. The nature of a buried interface prohibits the use of commonly used surface techniques. By the use of crystal truncation rod (CTR) x-ray scattering, it is possible to get information on the termination of the bulk silicon in a nondestructive fashion. The authors have investigated the influence of different cleanings on interfacial roughness using synchrotron radiation-based CTR-scattering. In particular, we looked at silicon(001) wafers both before and after the growth of a 1000Å thermal oxide. The results show that the use of HF during cleaning results in a smoother interface between silicon and its native oxide. Due to smoothing of the interface during the oxidation process, the difference between the various cleaning methods becomes less significant for these thick oxides.

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