Large-Grain Polysilicon Films with Low Intragranular Defect Density by Low-Temperature Solid-Phase Crystallization

2002 ◽  
Vol 715 ◽  
Author(s):  
Xiang-Zheng Bo ◽  
Nan Yao ◽  
J. C. Sturm
Keyword(s):  
Grain Size ◽  
Defect Density ◽  
Solid Phase ◽  
Solid Phase Crystallization ◽  
Transmission Electron ◽  
Cantilever Structure ◽  
Order Of Magnitude ◽  
Polysilicon Films ◽  
Silicon Interface ◽  
Atomic Rearrangement

AbstractSolid phase crystallization (SPC) of a-Si: H at 600°C was investigated by transmission electron microscopy (TEM) and Raman spectroscopy in a cantilever structure, where the underlying SiO2 was removed prior to the crystallization. The absence of the underlying oxide leads to both a higher grain size and a lower intragranular defect density. The grain size increases from 0.6 μm in regions with the underlying oxide to 3.0 μm without the underlying oxide, and the intragranular defect density decreases one order of magnitude from ∼ 1011 cm-2 to ∼ 1010 cm-2. The improvements in material quality without the lower a-Si/SiO2 interface are thought to be due to a lower nucleation rate and a lower tensile stress with an easier silicon atomic rearrangement at the lower silicon interface.

TEM characterization of Au/Polysilicon interactions

1990 ◽  
Vol 48 (4) ◽  
pp. 650-651
Author(s):  
N. David Theodore ◽  
Leslie H. Allen ◽  
C. Barry Carter ◽  
James W. Mayer
Keyword(s):  
Solid Phase ◽  
Single Crystal Silicon ◽  
Chemical Vapor ◽  
Electrical Contacts ◽  
Silicon Substrates ◽  
Crystal Silicon ◽  
Transmission Electron ◽  
Polysilicon Films ◽  
The Stability

Metal/polysilicon investigations contribute to an understanding of issues relevant to the stability of electrical contacts in semiconductor devices. These investigations also contribute to an understanding of Si lateral solid-phase epitactic growth. Metals such as Au, Al and Ag form eutectics with Si. reactions in these metal/polysilicon systems lead to the formation of large-grain silicon. Of these systems, the Al/polysilicon system has been most extensively studied. In this study, the behavior upon thermal annealing of Au/polysilicon bilayers is investigated using cross-section transmission electron microscopy (XTEM). The unique feature of this system is that silicon grain-growth occurs at particularly low temperatures ∽300°C).Gold/polysilicon bilayers were fabricated on thermally oxidized single-crystal silicon substrates. Lowpressure chemical vapor deposition (LPCVD) at 620°C was used to obtain 100 to 400 nm polysilicon films. The surface of the polysilicon was cleaned with a buffered hydrofluoric acid solution. Gold was then thermally evaporated onto the samples.

Solute Segregation and Dynamics of Solid-Phase Crystallization In in and Sb-Implanted Silicon

1981 ◽  
Vol 4 ◽  
Author(s):  
J. Narayan ◽  
G. L. Olson ◽  
O. W. Holland
Keyword(s):  
Laser Power ◽  
Solid Phase ◽  
Solute Segregation ◽  
Dislocation Loops ◽  
Solid Phase Crystallization ◽  
Time Resolved ◽  
Plan View ◽  
Ion Channeling ◽  
Retrograde Solubility ◽  
Transmission Electron

ABSTRACTTime-resolved-reflectivity measurements have been combined with transmission electron microscopy (cross-section and plan-view), Rutherford backscattering and ion channeling techniques to study the details of laser induced solid phase epitaxial growth in In+ and Sb+ implanted silicon in the temperature range from 725 to 1500 °K. The details of microstructures including the formation of polycrystals, precipitates, and dislocations have been correlated with the dynamics of crystallization. There were limits to the dopant concentrations which could be incorporated into substitutional lattice sites; these concentrations exceeded retrograde solubility limits by factors up to 70 in the case of the Si-In system. The coarsening of dislocation loops and the formation of a/2<110>, 90° dislocations in the underlying dislocation-loop bands are described as a function of laser power.

Solid-phase crystallization of ultra-thin amorphous Ge layers on insulators

2021 ◽  
Author(s):  
Ryo Oishi ◽  
Koji ASAKA ◽  
Bolotov Leonid ◽  
Noriyuki Uchida ◽  
Masashi Kurosawa ◽  
...  
Keyword(s):  
Grain Size ◽  
Grain Boundary ◽  
Barrier Height ◽  
Carrier Mobility ◽  
Solid Phase ◽  
Hole Mobility ◽  
Solid Phase Crystallization ◽  
Simple Method ◽  
20 Nm ◽  
Grain Boundary Barrier

Abstract A simple method to form ultra-thin (< 20 nm) semiconductor layers with a higher mobility on a 3D-structured insulating surface is required for next-generation nanoelectronics. We have investigated the solid-phase crystallization of amorphous Ge layers with thicknesses of 10−80 nm on insulators of SiO2 and Si3N4. We found that decreasing the Ge thickness reduces the grain size and increases the grain boundary barrier height, causing the carrier mobility degradation. We examined two methods, known effective to enhance the grain size in the thicker Ge (>100 nm). As a result, a relatively high Hall hole mobility (59 cm2/Vs) has been achieved with a 20-nm-thick polycrystalline Ge layer on Si3N4, which is the highest value among the previously reported works.

Stress and Dopant Activation in Solid Phase Crystalized Si Films

1999 ◽  
Vol 558 ◽  
Author(s):  
A. Kaan Kalkan ◽  
Stephen J. Fonash
Keyword(s):  
Tensile Stress ◽  
Defect Density ◽  
Solid Phase ◽  
Structural Defects ◽  
Raman Shift ◽  
Solid Phase Crystallization ◽  
Dopant Activation ◽  
Defect Creation ◽  
Si Films ◽  
High Level

ABSTRACTDefect creation mechanisms during solid phase crystallization (SPC) of Si thin films were investigated with PECVD amorphous precursor samples produced with various deposition temperatures and thicknesses. These precursor films were implanted with dopant and then crystallized to obtain both SPC and dopant activation. The doping efficiency was found to decrease with the tensile stress level as measured by Raman shift. The stress shows a decrease as the precursor deposition temperature and thickness are lowered. Furthermore, a lower level of stress is induced by rapid thermal annealing when the annealing temperature is high enough to soften the glass substrate on which the films were deposited. We show that by control of stress during the SPC step, intragrain defect density can be lowered and electronic quality of the resulting polycrystalline Si films can be improved. Based on these observations, we propose the following tentative model to explain the defect creation: during SPC, tensile stress evolution is considered to result from the volumetric contraction of Si film when it transforms from the amorphous to crystalline phase. This contraction is retarded by the substrate, which imposes a tensile stress on the film. A high level of stress leads to formation of structural defects inside the grains of the resulting polycrystalline material. These defects trap carriers or complex with the dopant reducing doping efficiency.

Grain size, Grain Uniformity, and (111) Texture Enhancement by Solid-phase Crystallization of F- and C-implanted SiGe Films

2000 ◽  
Vol 15 (7) ◽  
pp. 1630-1634 ◽  
Author(s):  
A. Rodríguez ◽  
J. Olivares ◽  
C. González ◽  
J. Sangrador ◽  
T. Rodríguez ◽  
...  
Keyword(s):  
Grain Size ◽  
Vapor Deposition ◽  
Solid Phase ◽  
Chemical Vapor ◽  
Solid Phase Crystallization ◽  
Grain Sizes ◽  
Pressure Chemical ◽  
Film Microstructure ◽  
Si Films ◽  
Size Dispersion

The crystallization kinetics and film microstructure of poly-SiGe layers obtained by solid-phase crystallization of unimplanted and C- and F-implanted 100-nm-thick amorphous SiGe films deposited by low-pressure chemical vapor deposition on thermally oxidized Si wafers were studied. After crystallization, the F- and C-implanted SiGe films showed larger grain sizes, both in-plane and perpendicular to the surface of the sample, than the unimplanted SiGe films. Also, the (111) texture was strongly enhanced when compared to the unimplanted SiGe or Si films. The crystallized F-implanted SiGe samples showed the dendrite-shaped grains characteristic of solid-phase crystallized pure Si. The structure of the unimplanted SiGe and C-implanted SiGe samples consisted of a mixture of grains with well-defined contour and a small number of quasi-dendritic grains. These samples also showed a very low grain-size dispersion.

Solid-Phase Crystallization of a-Si:H by RTA

2010 ◽  
Vol 44-47 ◽  
pp. 4151-4153 ◽  
Author(s):  
Rui Min Jin ◽  
Ding Zhen Li ◽  
Lan Li Chen ◽  
Xiang Ju Han ◽  
Jing Xiao Lu
Keyword(s):  
Thin Film ◽  
Grain Size ◽  
Amorphous Silicon ◽  
Glass Substrate ◽  
Solid Phase ◽  
X Ray Diffraction ◽  
Solid Phase Crystallization ◽  
X Ray ◽  
Average Grain Size ◽  
Electronic Microscope

Amorphous silicon films prepared by PECVD on glass substrate has been crystallized by rapid thermal annealing (RTA) at the same temperature for different time. From X-ray diffraction (XRD) and scanning electronic microscope (SEM), it is found that the grain size is biggest crystallized at 720°C for 8 min, an average grain size of 28nm or so is obtained. The thin film is smoothly and perfect structure.

scholarly journals Solid-phase crystallization under continuous heating: Kinetic and microstructure scaling laws

2008 ◽  
Vol 23 (2) ◽  
pp. 418-426 ◽  
Author(s):  
J. Farjas ◽  
P. Roura
Keyword(s):  
Grain Size ◽  
Kinetic Parameters ◽  
Scaling Laws ◽  
Solid Phase ◽  
Scaling Law ◽  
Continuous Heating ◽  
Dimensionless Time ◽  
Solid Phase Crystallization ◽  
Average Grain Size ◽  
Length Scaling

The kinetics and microstructure of solid-phase crystallization under continuous heating conditions and random distribution of nuclei are analyzed. An Arrhenius temperature dependence is assumed for both nucleation and growth rates. Under these circumstances, the system has a scaling law such that the behavior of the scaled system is independent of the heating rate. Hence, the kinetics and microstructure obtained at different heating rates differ only in time and length scaling factors. Concerning the kinetics, it is shown that the extended volume evolves with time according to αex = [exp(κCt′)]m+1, where t′ is the dimensionless time. This scaled solution not only represents a significant simplification of the system description, it also provides new tools for its analysis. For instance, it has been possible to find an analytical dependence of the final average grain size on kinetic parameters. Concerning the microstructure, the existence of a length scaling factor has allowed the grain-size distribution to be numerically calculated as a function of the kinetic parameters.

Defect Reduction in Laser Thermal Processing

2000 ◽  
Vol 610 ◽  
Author(s):  
Heather Banisaukas ◽  
Kevin S. Jones ◽  
Somit Talwar ◽  
Scott Falk ◽  
Dan F. Downey
Keyword(s):  
Dose Rate ◽  
Thermal Processing ◽  
Defect Density ◽  
Solid Phase ◽  
Amorphous Layer ◽  
Beam Current ◽  
Interface Roughness ◽  
Molten Layer ◽  
Order Of Magnitude ◽  
Laser Thermal Processing

AbstractLaser thermal processing (LTP) of Si involves laser melting a preamorphized layer in order to activate dopants and create a low resistivity contact. Defects are often observed to form during the recrystallization of the molten layer. This work focuses on varying the implant conditions and the pre-LTP annealing conditions in an effort to reduce these defect concentrations. The effect of very low temperature anneals (VLTA) and varying dose rates on the amorphous/crystalline interface roughness prior to LTP and the defect density after LTP have been investigated. The amorphous layer was created by a 10 keV 1×1015/cm2 Si+ implant. VLTA were conducted in a nitrogen gas furnace at temperatures between 400°C and 450°C for times between 5 minutes and 60 minutes. These anneals were chosen to minimize recrystallization of the amorphous layer by solid phase epitaxial regrowth. Variation in the dose rate from 0.06 mA/cm2 to 0.48 mA/cm2 was achieved by changing the beam current in the ion implanter. High-resolution crosssectional transmission electron microscopy (HR-XTEM) was used to analyze the effect of the VLTA or dose rate on the amorphous/crystalline interface. Results show that the 400°C 60 minute VLTA or the 0.48 mA/cm2 dose rate reduced the roughness of the amorphous/crystalline interface from over 45Å to around 15Å. This reduction in amorphous/crystalline interface roughness prior to laser thermal processing results in a reduction in LTP recrystallization defects by as much as an order of magnitude.

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