Interface Adhesion and Reliability of Microsystem Packaging

2003 ◽  
Vol 782 ◽  
Author(s):  
Marvin I. Francis ◽  
Kellen Wadach ◽  
Satyajit Walwadkar ◽  
Junghyun Cho
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Dissimilar Materials ◽  
Strain Energy Release ◽  
Interface Adhesion ◽  
Curing Conditions ◽  
Chip Technology ◽  
Solder Balls ◽  
Cte Mismatch

ABSTRACTFlip-chip technology is becoming one of the most promising packaging techniques for high performance packages. Solder balls are used as the connection technique in the flip-chip method and the connections are reinforced by filling in the spacing between the chip and substrate with underfill. The function of the underfill is to reduce the stresses in the solder joints caused by a coefficient of thermal expansion (CTE) mismatch. The presence of polymeric underfill material will, however, make the flip-chip packaging system susceptible to interfacial failure. Thus, the purpose of this study is to examine the interfacial delamination between the dissimilar materials in order to increase the reliability of the flip-chip interconnection method, and to understand the effect of underfill curing conditions on the interface adhesion. In particular, we use a linear elastic fracture mechanics (LEFM) approach to assess interfacial toughness. For this purpose, four-point bending testing is performed to determine a critical strain energy release rate, Gc. In addition, nano-indentation testing equipped with atomic force microscope (AFM) is employed to determine structure and properties of the underfill layer.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Effect of Design Factors on Microvia Reliability of Flip Chip Ball Grid Array Polymeric Substrates

2008 ◽  
Vol 5 (3) ◽  
pp. 104-115
Author(s):  
Dennis Leung ◽  
Guna Selvaduray
Keyword(s):  
Electrical Resistance ◽  
High Performance ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Temperature Cycling ◽  
Low Aspect Ratio ◽  
Cte Mismatch ◽  
Polymeric Substrates ◽  
Design Factors ◽  
The Relationship

Microvia failures in flip chip ball grid array (FCBGA) polymeric substrates have been a major concern in the development of reliable packages for high-performance and high-density chips. To determine the relationship between reliability and design factors of the microvias, a 10-layer substrate was used to investigate these contrasting design factors: “stack-on-core” vs. “non–stack-on-core,” “high” vs. “low” aspect ratio, “stacked” vs. “staggered,” and “fillet” vs. “non-fillet.” Temperature cycling was used to generate stresses on the microvias. Electrical resistance was measured and analyzed, using design of experiment (DOE), to determine the effects of these design factors on microvia reliability. The significant single factors for a robust microvia were “non–stack-on-core” and “staggered.” Cross-sectioning was employed to understand the failure pattern. Cracks occurred on “stack-on-core” and “stacked” designs only. All the cracks were located at the interface between the capture pad and the bottom of the microvia, where stress is the highest due to the CTE mismatch of different materials.

Lightweight Hybrid Foam with Dimensional Stability

2010 ◽  
Vol 63 ◽  
pp. 114-119
Author(s):  
Ming Yung Chen ◽  
Cheng Gang Chen
Keyword(s):  
Dimensional Stability ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Synergistic Effects ◽  
Dissimilar Materials ◽  
Porous Ceramics ◽  
Thermomechanical Analysis ◽  
Environmental Stability ◽  
Advanced Materials ◽  
Functional Requirements

Availability of advanced materials has opened up opportunities in meeting several functional requirements through hybridization. Hybrids consisting of ceramics, metals and high performance polymers could benefit many aircraft and space satellite applications. They could meet requirements of low weight, high environmental stability, and high thermal or dimensional stability. In this study, hybrid materials consisting of high performance polymer, porous ceramics (glass microballoons) and other constituents such as Zircornium Tungstate (with negative coefficient of thermal expansion (CTE)) and nanoclay were studied. Specimens were successfully produced with a range of density from 0.4 to 1.1 g/cm3 depending on the degree of fill in the syntactic foams. CTE tailoring was achieved to greatly reduce the residual stress arising from processing and CTE mismatch of dissimilar materials. The evaluations of dimensional stability were examined from thermomechanical analysis. The synergistic effects of resin, ceramic constituents and pores on the hybrid properties will be presented.

Solder Joint Reliability Assessment for a High Performance RF Ceramic Package

2014 ◽  
Vol 2014 (1) ◽  
pp. 000062-000067 ◽  
Author(s):  
Paul Charbonneau ◽  
Hans Ohman ◽  
Marc Fortin
Keyword(s):  
Solder Joint ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Unit Cost ◽  
Reliability Assessment ◽  
Lead Free ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Cte Mismatch ◽  
Life Predictions

The prediction of long term solder joint reliability, (SJR), of microelectronic devices and packaging solutions continues to challenge the microelectronic packaging industry, particularly with the introduction of lead-free materials, the push for higher performance (frequency/speed/thermal) and lower unit cost. High performance packages are generally custom designed and therefore have minimal industry data on configuration specific reliability performance. In this application, the package substrate coefficient of thermal expansion, (CTE), was closely matched to the die resulting in a relatively large CTE mismatch between the package and organic PCB. In addition, the package RF and thermal performance requirements required this particular solution to be configured as a “cavity down” perimeter ball array with a large central ground pad to electrically couple the package to the PCB. Given the package's unique design requirements and CTE mismatch, even modest daily temperature swings of 20°C usually found in a controlled or “Central Office” environment could have an adverse impact on the interconnect reliability. This study provides an overview of the solder joint reliability assessment methodologies performed for a custom design lead-free, high performance RF package as part of the requirements to demonstrate compliance to product specifications. SJR life predictions were made for varying package BGA configurations using a multi-tiered approach using constitutive material models, thermo-mechanical finite element simulations, and material specific fatigue models. Empirical accelerated life testing was performed and a life prediction obtained through modeling was validated. Finally, statistical failure distributions were fit to empirical data and discussed in the context of absolute solder life predictions of small fractions unit failures, (100ppm).

Interactions between Variable Frequency Microwave Underfill Processing and High Performance Packaging Materials

2013 ◽  
Vol 2013 (1) ◽  
pp. 000461-000466 ◽  
Author(s):  
Mamadou Diobet Diop ◽  
Marie-Claude Paquet ◽  
Dominique Drouin ◽  
David Danovitch
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Curing Temperature ◽  
Variable Frequency ◽  
Asymmetric Distribution ◽  
Unexpected Result ◽  
Scanning Calorimetry ◽  
Negative Effect ◽  
Curing Methods

Variable frequency microwave (VFM) has been recently proposed as an alternative underfill curing method that provides flip chip package warpage improvement as well as potential underfill cure time reductions. The current paper outlines how such advantages in VFM processing of underfill can be compromised when applied to high performance organic packages. VFM recipes for three underfill materials were developed by performing several VFM curing runs followed by curing rate measurements using the differential scanning calorimetry method. The VFM curing rate was seen to strongly dependent upon the underfill chemistry. By testing flip chip parts that comprised large and high-end substrates, we showed that the underfill material has negligible impact on VFM warpage with the major cause attributed to the coefficient of thermal expansion mismatch between the die and the substrate. Comparison between the convection and the VFM methods indicated two warpage tendencies that depended upon the VFM curing temperature. First, when both curing methods used comparably high temperatures, warpage increases up to about + 20% were found with VFM. This unexpected result was explained by the high-density Cu loading of the substrate which systematically carried heat generated by VFM energy from the die/underfill system to the substrate. Since this high-end substrate consists of sequential dielectric/Cu layers with asymmetric distribution of Cu, additional stresses due to local CTE mismatches between the Cu and the dielectric layers were induced within the substrate processed with VFM. Second, warpage reductions down to about − 22% were obtained at the VFM curing temperature of 110°C with a curing time similar to that of convection cure. This suggests that the negative effect of the local CTE mismatches were no longer at play at the lower VFM temperatures and that the significantly lower final cure temperatures produced lower total shrinkage of the die and the substrate. Finally, due to lower elastic moduli, the cured VFM parts showed better mechanical reliability with no fails up to 1500 cycles.

Reliability Prediction of Area Array Solder Joints

2003 ◽  
Vol 125 (4) ◽  
pp. 562-568 ◽  
Author(s):  
Rainer Dudek ◽  
Ralf Do¨ring ◽  
Bernd Michel
Keyword(s):  
Geometric Modeling ◽  
Flip Chip ◽  
Failure Criteria ◽  
Temperature Fields ◽  
The Finite Element Method ◽  
Chip Technology ◽  
Array Technology ◽  
Chip Scale Package ◽  
Solder Balls

Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogeneity of the cyclic temperature fields, simplified creep characterization of solder, and the related application of Manson-Coffin failure criteria, are discussed in the paper. The packages chosen for detailed analyses are a PBGA 272 and a FC-CSP 230.

Design Features of Compliant Packages and Their Impact on Reliability

2001 ◽  
Author(s):  
Ilyas Mohammed ◽  
Young-Gon Kim
Keyword(s):  
Flip Chip ◽  
High Reliability ◽  
Electronic Packages ◽  
Detailed Design ◽  
Testing Data ◽  
Solder Balls ◽  
Cte Mismatch ◽  
The Difference ◽  
Electrical Connections ◽  
Package Reliability

Abstract It is well-known that the main cause of mechanical failure in electronic packages is due to the difference in the Coefficients of Thermal Expansion (CTE) of the silicon and the organic board. There are many packaging technologies that try to overcome this limitation; ranging from making curved connection pins (gull-wing leads) from the package to the board, as in the case of Thin Small Outline Package (TSOP), to using hard epoxy to rigidly adhere the die to the board as in the case of flip-chip packages. This paper illustrates a compliant packaging concept that minimizes the effect of the CTE mismatch between the silicon die and the board. A summary of different packaging techniques that address the CTE mismatch problem is presented. From this summary, it is apparent that many of these techniques do not provide as high reliability as the compliant packages do, especially when the electrical connections from the package to the board (solder balls) are present directly under the silicon die as in the case of chip scale packages. As the compliant package isolates the effect of the silicon die from the substrate, the silicon has some motion relative to the substrate. This means that the interconnections from the silicon to the substrate must be designed to withstand this motion. Hence the design of these interconnections is key to maximizing the reliability of the compliant packages. A detailed design and reliability analysis of compliant packages for different applications is presented. The design highlights the main parameters that have an effect on reliability of the package. Reliability simulation and analysis using finite element techniques is presented for different designs to highlight the key parameters that govern the reliability of compliant packages. Finally, reliability testing data is presented for different packages.

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

2018 ◽  
Vol 2018 (1) ◽  
pp. 000270-000276 ◽  
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Ivor Barber
Keyword(s):  
Integrated Circuit ◽  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Leading Edge ◽  
Lead Free ◽  
Assembly Process ◽  
Chip Technology ◽  
Layer Deposition ◽  
Ic Package

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000618-000634 ◽  
Author(s):  
Rabindra Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

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