Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Development of Organic Multi Chip Package for High Performance Application

2013 ◽  
Vol 2013 (1) ◽  
pp. 000414-000414 ◽  
Author(s):  
Noriyoshi Shimizu ◽  
Wataru Kaneda ◽  
Hiromu Arisaka ◽  
Naoyuki Koizumi ◽  
Satoshi Sunohara ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Metal Layer ◽  
Small Diameter ◽  
Organic Substrate ◽  
Back Side ◽  
Test Results ◽  
Manufacturing Method ◽  
Separate Step ◽  
High Performance Application

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.

Interface Adhesion and Reliability of Microsystem Packaging

2003 ◽  
Vol 782 ◽  
Author(s):  
Marvin I. Francis ◽  
Kellen Wadach ◽  
Satyajit Walwadkar ◽  
Junghyun Cho
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Dissimilar Materials ◽  
Strain Energy Release ◽  
Interface Adhesion ◽  
Curing Conditions ◽  
Chip Technology ◽  
Solder Balls ◽  
Cte Mismatch

ABSTRACTFlip-chip technology is becoming one of the most promising packaging techniques for high performance packages. Solder balls are used as the connection technique in the flip-chip method and the connections are reinforced by filling in the spacing between the chip and substrate with underfill. The function of the underfill is to reduce the stresses in the solder joints caused by a coefficient of thermal expansion (CTE) mismatch. The presence of polymeric underfill material will, however, make the flip-chip packaging system susceptible to interfacial failure. Thus, the purpose of this study is to examine the interfacial delamination between the dissimilar materials in order to increase the reliability of the flip-chip interconnection method, and to understand the effect of underfill curing conditions on the interface adhesion. In particular, we use a linear elastic fracture mechanics (LEFM) approach to assess interfacial toughness. For this purpose, four-point bending testing is performed to determine a critical strain energy release rate, Gc. In addition, nano-indentation testing equipped with atomic force microscope (AFM) is employed to determine structure and properties of the underfill layer.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Reliability Prediction of Area Array Solder Joints

2003 ◽  
Vol 125 (4) ◽  
pp. 562-568 ◽  
Author(s):  
Rainer Dudek ◽  
Ralf Do¨ring ◽  
Bernd Michel
Keyword(s):  
Geometric Modeling ◽  
Flip Chip ◽  
Failure Criteria ◽  
Temperature Fields ◽  
The Finite Element Method ◽  
Chip Technology ◽  
Array Technology ◽  
Chip Scale Package ◽  
Solder Balls

Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogeneity of the cyclic temperature fields, simplified creep characterization of solder, and the related application of Manson-Coffin failure criteria, are discussed in the paper. The packages chosen for detailed analyses are a PBGA 272 and a FC-CSP 230.

Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Ronald Hon
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Back Side ◽  
Wafer Level ◽  
Flip Chips ◽  
Electrical Interconnection ◽  
Solder Balls ◽  
Original Size ◽  
Structure Lead ◽  
Silicon Vias

ABSTRACTThe study is a prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs for interconnection. Three chips are stacked together to make a 3DP with solder bumped flip chips. TSVs are fabricated and distributed along the periphery of the middle chip. The TSVs are formed by dry etching, deep reactive ions etching (DRIE), with dimensions of 150 × 100 microns. The TSVs are plugged by copper plating. The filled TSVs are connected to the solder pads by extended pad patterns surrounding the top and the bottom of TSVs on both sides of the wafer for the middle chip. After pad patterning passivation and solder bumping, the wafer is sawed into chips for subsequent 3D stacked die assembly. Because the TSVs are located at the periphery of the middle chips and stretch across the saw street between adjacent chips, they will be sawed through their center to form two open TSVs (with half of the original size) for electrical interconnection between the front side and the back side of the middle chip. The top chip is made by the conventional solder bumped flip chip processes and the bottom chip is a carrier with some routing patterns. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented.

Interfacial Morphology and Shear Deformation of Flip Chip Solder Joints

2000 ◽  
Vol 15 (8) ◽  
pp. 1679-1687 ◽  
Author(s):  
J. W. Jang ◽  
C. Y. Liu ◽  
P. G. Kim ◽  
K. N. Tu ◽  
A. K. Mal ◽  
...  
Keyword(s):  
Shear Deformation ◽  
Dielectric Layer ◽  
Flip Chip ◽  
Solder Joints ◽  
Organic Substrate ◽  
Failure Behavior ◽  
Interfacial Morphology ◽  
Solder Interconnects ◽  
Solder Balls ◽  
Electroless Ni

We examined the interfacial morphology and shear deformation of flip chip solder joints on an organic substrate (chip-on-board). The large differences in the coefficients of thermal expansion between the board and the chip resulted in bending of the 1-cm2 chip with a curvature of 57 ± 12 cm. The corner bump pads on the chip registered a relative misalignment of 10 μm with respect to those on the board, resulting in shear deformation of the solder joints. The mechanical properties of these solder joints were tested on samples made by sandwiching two Si chips with electroless Ni(P) as the under-bump metallization and 25 solder interconnects. Joints were sheared to failure. Fracture was found to occur along the solder/Ni3Sn4 interface. In addition, cracking and peeling damages of the SiO2 dielectric layer were observed in the layer around the solder balls, indicating that damage to the dielectric layer may have occurred prior to the fracture of the solder joints due to a large normal stress. The failure behavior of the solder joints is characterized by an approximate stress analysis.

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

2018 ◽  
Vol 2018 (1) ◽  
pp. 000270-000276 ◽  
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Ivor Barber
Keyword(s):  
Integrated Circuit ◽  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Leading Edge ◽  
Lead Free ◽  
Assembly Process ◽  
Chip Technology ◽  
Layer Deposition ◽  
Ic Package

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000618-000634 ◽  
Author(s):  
Rabindra Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

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