Designing and Modeling of Logic Circuits Based on Switching of the Gated Oligo-Phenylenevinylene Molecule

2017 ◽  
Vol 46 ◽  
pp. 82-92 ◽  
Author(s):  
Saleh Safapour ◽  
Reza Sabbaghi-Nadooshan ◽  
Ali Asghar Shokri
Keyword(s):  
Molecular Electronics ◽  
Field Effect Transistors ◽  
Circuit Simulation ◽  
Logic Gates ◽  
Full Adder ◽  
Logic Circuits ◽  
Simulation Software ◽  
Molecular Systems ◽  
Half Adder ◽  
The Cost

Molecular electronics seeks to decrease the cost, power consumption and size of devices, using a variety of approaches. However, few attempts have been made to address circuit simulation. The availability of common semiconductor components means they can be used for modeling and simulating molecular circuits to speed progress in molecular electronics. The present study examines the switching of a gated oligo-phenylenevinylene (OPV) molecule as a NMOS molecular transistor, resistance as an indicator of methyl molecules, and the linking of these abilities using LTspice simulation software. The circuit simulation of molecules of basic logic gates, half-adder, full-adder, and multiplier logic circuits are carried out. The numerical results may shed light on the next applications of molecular systems and make them a good, promising candidate for field-effect transistors.

Three-leg molecular transistors as molecular logic circuits: Design and modeling

2018 ◽  
Vol 32 (22) ◽  
pp. 1850234
Author(s):  
Aliasghar Shokri ◽  
Saleh Safapour ◽  
Reza Sabbaghi-Nadooshan
Keyword(s):  
Molecular Electronics ◽  
Full Adder ◽  
Logic Circuits ◽  
Simulation Software ◽  
Molecular Logic ◽  
Half Adder ◽  
Molecular Transistors ◽  
Transistor Model ◽  
Silicon Based ◽  
Molecular Transistor

The field of molecular electronics is a branch of science, which can have a variety of semiconductor technologies that extend beyond the silicon-based technology for the future. This branch of science may solve the limitations on size, high power usage and low speed in semiconductor technology. Rapid improvements in molecular electronics require modeling in the design of molecular devices. In this regard, we examine a three-leg molecule as a molecular transistor model and an indicator of methyl molecule as a resistance, in which the linkage of these abilities is carried out using LTspice simulation software. In order to investigate the effect of gated molecular on transport properties of the device, we design the half-adder molecular circuit and full-adder molecular circuit with them. The feasibility of building a prototype molecular transistor is illustrated using three-leg molecules directly contacted to gold electrodes, which the transmitted current from the structure is calculated using the Landauer formula. The application of the predicted results can be a base for designing moletronics devices.

Structural characterization of a fluorescein hydrazone molecular switch with application towards logic gates

2018 ◽  
Vol 42 (22) ◽  
pp. 18050-18058 ◽  
Author(s):  
Juan D. Villada ◽  
Richard F. D’Vries ◽  
Mario Macías ◽  
Fabio Zuluaga ◽  
Manuel N. Chaur
Keyword(s):  
Structural Characterization ◽  
Metal Cations ◽  
Logic Gates ◽  
Molecular Switch ◽  
Logic Circuits ◽  
X Ray ◽  
Ph Changes ◽  
X Ray Crystallography ◽  
Half Adder

A new polymorph of fluorescein hydrazone was fully characterized via single X-ray crystallography. In addition, multiple logic circuits and a Half-Adder operator were designed using the fluorescence and UV-Vis switching responses of the fluorescein compound to different metal cations and pH changes.

SPATIAL WAVEFUNCTION-SWITCHED (SWS)-FET: A NOVEL DEVICE TO PROCESS MULTIPLE BITS SIMULTANEOUSLY WITH SUB-PICOSECOND DELAYS

2011 ◽  
Vol 20 (03) ◽  
pp. 641-652 ◽  
Author(s):  
F. C. JAIN ◽  
J. CHANDY ◽  
B. MILLER ◽  
E-S. HASANEEN ◽  
E. HELLER
Keyword(s):  
Quantum Wells ◽  
Field Effect Transistors ◽  
Logic Gates ◽  
Spatial Location ◽  
Full Adder ◽  
Channel Length ◽  
Coupled Quantum Wells ◽  
Quantum Well Structures ◽  
Novel Device ◽  
Capacitance Voltage

Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs - AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n -channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.

scholarly journals Energy Efficient Tri-State CNFET Ternary Logic Gates

2018 ◽  
Author(s):  
Sepher Tabrizchi ◽  
Fazel Sharifi ◽  
Abdel-Hameed A. Badawy
Keyword(s):  
Carbon Nanotube ◽  
Field Effect Transistors ◽  
Logic Gates ◽  
Logic Circuits ◽  
Ternary Logic ◽  
Large Area ◽  
Logic Function ◽  
Correct Operation ◽  
Power Efficient ◽  
Simulation Results

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano-devices are two feasible solutions to overcome these problems. In this paper, we present a novel method to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, e.g., adjusting the Carbon Nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. We show a more detailed application of our approach by designing a two-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, we designed a two-digit adder/subtractor and a power efficient ternary logic ALU based on the proposed gates. Simulation results show that the two-digit adder/subtractor using our proposed gates has 12X and 5X lower power consumption and PDP (power delay product) respectively, compared to previous designs.

New Adders Using Hybrid Circuit Consisting of Three-Gate Single-Electron Transistors (TG-SETs) and MOSFETs

2007 ◽  
Vol 7 (11) ◽  
pp. 4120-4125
Author(s):  
Yunseop Yu ◽  
Jungbum Choi
Keyword(s):  
Field Effect Transistors ◽  
Circuit Simulation ◽  
Average Power ◽  
Single Electron ◽  
Oxide Semiconductor ◽  
Single Electron Transistors ◽  
Worst Case ◽  
Half Adder ◽  
Average Power Consumption ◽  
Electron Transistors

A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional CMOS FA with 0.35 μm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs.

scholarly journals Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder

2021 ◽  
Vol 5 (1) ◽  
pp. 1-7
Author(s):  
S. MOHAN DAS ◽  
GANESH KUMAR M ◽  
BHASKARA RAO K
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Universal Logic ◽  
Significant Saving ◽  
Low Leakage ◽  
Low Threshold ◽  
The Cost

This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.

Evolution of Adder and Subtractor Circuit Using Si3N4 Microring Resonator

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Ankur Saharia ◽  
Ashish Kumar Ghunawat ◽  
Manish Tiwari ◽  
Anton V. Bourdine ◽  
Vladimir A. Burdin ◽  
...  
Keyword(s):  
Numerical Simulations ◽  
Logic Gates ◽  
Full Adder ◽  
Microring Resonator ◽  
Microring Resonators ◽  
Basic Logic ◽  
Combinational Circuit ◽  
Half Adder ◽  
All Optical ◽  
Optical Processor

AbstractAll-optical processor capable of processing optical bits has been a long-standing goal of photonics. In this paper, we report the results obtained by numerical simulations regarding the designing of an all-optical combinational circuit of an adder and subtractor circuits based on Si3N4 microring resonators. The designs of combinational circuit like adders and subtractor based on the use of all-optical basic logic gates are discussed while presenting the numerically simulated results. Extinction ratios of 5.2 dB, 3.5 dB and 2.7 dB are obtained for the half adder, full adder and half subtractor, respectively.

HAMILTONIAN LOGIC GATES: COMPUTING INSIDE A MOLECULE

2005 ◽  
Vol 04 (01) ◽  
pp. 107-118 ◽  
Author(s):  
C. JOACHIM ◽  
I. DUCHEMIN ◽  
J. FIURÁŠEK ◽  
N. J. CERF
Keyword(s):  
Molecular Electronics ◽  
Single Molecule ◽  
Logic Gate ◽  
Level Structure ◽  
Logic Gates ◽  
Electrical Circuit ◽  
Molecular Logic ◽  
Molecular Logic Gates ◽  
Half Adder ◽  
Nonstationary State

Using an intramolecular single-electron transfer process, we show how computing inside a quantum system can be performed using the time evolution driven by the preparation of the system in a nonstationary state. The molecule Hamiltonian is separated in three parts: the input, calculation, and output parts. Two optimization procedures are described in order to design an efficient monoelectronics level structure for molecular logic gates. An XOR gate and a half-adder using six electronic quantum levels are presented in a prospect to integrate a full logic gate inside a single molecule without forcing the molecule to have the shape of an electrical circuit. We foresee the merger of molecular electronics with quantum computation at the nanoscale.

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