scholarly journals A High-resolution Colloidal Quantum Dot Imager by Monolithic Integration

2021 ◽  
Author(s):  
Jing Liu ◽  
Peilin Liu ◽  
Dengyang Chen ◽  
Tailong Shi ◽  
Xixi Qu ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Flip Chip ◽  
Near Infrared ◽  
Dynamic Range ◽  
Low Cost ◽  
Monolithic Integration ◽  
Oxide Semiconductor ◽  
Modulation Transfer ◽  
Readout Integrated Circuit

Abstract Near-infrared (NIR, 0.7–1.4 µm) imagers have wide applications in night surveillance, material sorting, machine vision and potentially automatic driving. However, limited by the high-temperature processing and requirement of single-crystalline substrate, so far flip-chip is the dominant way to connect infrared photodiodes and silicon-based readout integrated circuit (ROIC) to produce infrared imagers, suffering from complicated process and ultra-high cost and hence limiting their widespread applications in the market. Here we report the monolithic integration of colloidal quantum dots (CQD) photodiodes with complementary metal-oxide-semiconductor (CMOS) ROIC, operating as a low-cost and high-performance imager. The CQD photodetector is well designed with a CMOS-compatible structure, demonstrating a response spectral range of 400–1300 nm, a detectivity of 2.1×1012 Jones at room temperature, a -3dB bandwidth of 140 kHz and a linear dynamic range over 100 dB. The CQD imager can identify materials, inspect apple scar and veins with a large size of 640×512 pixels and a spatial resolution of 40 lp/mm at a modulation transfer function of 50%. Monolithic integration significantly reduces the cost without sacrificing performance, thus providing huge potential for the ubiquitous deployment of infrared imagers.

scholarly journals Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3370 ◽  
Author(s):  
Saghi Forouhi ◽  
Rasoul Dehghani ◽  
Ebrahim Ghafar-Zadeh
Keyword(s):  
High Performance ◽  
Life Science ◽  
Dynamic Range ◽  
Current Mode ◽  
Capacitive Sensor ◽  
Oxide Semiconductor ◽  
Capacitance Measurement ◽  
Biological Research ◽  
Cmos Process ◽  
Capacitive Sensors

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

scholarly journals Process Design Kit and Design Automation for Flexible Hybrid Electronics

2019 ◽  
Vol 16 (3) ◽  
pp. 117-123
Author(s):  
Tsung-Ching Huang ◽  
Ting Lei ◽  
Leilai Shao ◽  
Sridhar Sivapurapu ◽  
Madhavan Swaminathan ◽  
...  
Keyword(s):  
Process Design ◽  
Design Automation ◽  
High Performance ◽  
Large Scale ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Solution Process ◽  
Oxide Semiconductor ◽  
Wearable Electronics ◽  
Wide Range

Abstract High-performance low-cost flexible hybrid electronics (FHE) are desirable for applications such as internet of things and wearable electronics. Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility, superior mechanical flexibility, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers, and sense amplifiers, can be printed and hybrid-integrated with thinned (<50 μm) silicon chips on soft, thin, and flexible substrates for a wide range of applications, from flexible displays to wearable medical devices. Here, we report (1) a process design kit (PDK) to enable FHE design automation for large-scale FHE circuits and (2) solution process-proven intellectual property blocks for TFT circuits design, including Pseudo-Complementary Metal-Oxide-Semiconductor (Pseudo-CMOS) flexible digital logic and analog amplifiers. The FHE-PDK is fully compatible with popular silicon design tools for design and simulation of hybrid-integrated flexible circuits.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

scholarly journals Up-Conversion Sensing of 2D Spatially-Modulated Infrared Information-Carrying Beams with Si-Based Cameras

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3610
Author(s):  
Adrián J. Torregrosa ◽  
Emir Karamehmedović ◽  
Haroldo Maestre ◽  
María Luisa Rico ◽  
Juan Capmany
Keyword(s):  
Optical Communications ◽  
Near Infrared ◽  
Nonlinear Crystal ◽  
Signal To Noise Ratio ◽  
Low Cost ◽  
Infrared Image ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Oxide Semiconductor ◽  
Free Space Optical

Up-conversion sensing based on optical heterodyning of an IR (infrared) image with a local oscillator laser wave in a nonlinear optical sum-frequency mixing (SFM) process is a practical solution to circumvent some limitations of IR image sensors in terms of signal-to-noise ratio, speed, resolution, or cooling needs in some demanding applications. In this way, the spectral content of an IR image can become spectrally shifted to the visible/near infrared (VIS/NWIR) and then detected with silicon focal plane arrayed sensors (Si-FPA), such as CCD/CMOS (charge-coupled and complementary metal-oxide-semiconductor devices). This work is an extension of a previous study where we recently introduced this technique in the context of optical communications, in particular in FSOC (free-space optical communications). Herein, we present an image up-conversion system based on a 1064 nm Nd3+: YVO4 solid-state laser with a KTP (potassium titanyl phosphate) nonlinear crystal located intra-cavity where a laser beam at 1550 nm 2D spatially-modulated with a binary Quick Response (QR) code is mixed, giving an up-converted code image at 631 nm that is detected with an Si-based camera. The underlying technology allows for the extension of other IR spectral allocations, construction of compact receivers at low cost, and provides a natural way for increased protection against eavesdropping.

scholarly journals Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

Nanophotonics ◽  
2017 ◽  
Vol 6 (6) ◽  
pp. 1343-1352 ◽  
Author(s):  
Chuantong Cheng ◽  
Beiju Huang ◽  
Xurui Mao ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Three Dimensional ◽  
Complementary Metal Oxide Semiconductor ◽  
Optical Signal ◽  
Optical Interconnect ◽  
Optical Receiver ◽  
Oxide Semiconductor ◽  
Experimental Realization ◽  
Operation Speed

AbstractOptical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

scholarly journals A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

2020 ◽  
Vol 10 (1) ◽  
pp. 399 ◽  
Author(s):  
Kwonsang Han ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Operational Amplifier ◽  
Wheatstone Bridge ◽  
Input Resistance ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Readout Integrated Circuit ◽  
Chopper Stabilization

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

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