Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits

Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

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TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100138713 ◽

1995 ◽

Vol 53 ◽

pp. 468-469

Author(s):

N. David Theodore ◽

Donald Y.C Lie ◽

J. H. Song ◽

Peter Crozier

Keyword(s):

Integrated Circuits ◽

Heterojunction Bipolar Transistors ◽

Integrated Circuit ◽

High Speed ◽

Room Temperature ◽

Strain Relaxation ◽

Bipolar Transistors ◽

Sige Hbt ◽

Integrated Circuit Manufacturing ◽

Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

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The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences ◽

10.3390/app11010429 ◽

2021 ◽

Vol 11 (1) ◽

pp. 429

Author(s):

Min-Su Kim ◽

Youngoo Yang ◽

Hyungmo Koo ◽

Hansik Oh

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Low Power ◽

High Speed ◽

Cmos Technology ◽

Clock Frequency ◽

Clock Generation ◽

Allocation Method ◽

Evaluation Board ◽

28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

MRS Proceedings ◽

10.1557/opl.2013.585 ◽

2013 ◽

Vol 1538 ◽

pp. 291-302

Author(s):

Edward Yi Chang ◽

Hai-Dang Trinh ◽

Yueh-Chin Lin ◽

Hiroshi Iwai ◽

Yen-Ku Lin

Keyword(s):

Low Power ◽

Leakage Current ◽

High Speed ◽

High Performance ◽

Gate Oxide ◽

Chemical Cleaning ◽

Low Leakage ◽

Low Leakage Current ◽

High K ◽

Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

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Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

International Journal of Nanoscience ◽

10.1142/s0219581x14500124 ◽

2014 ◽

Vol 13 (02) ◽

pp. 1450012 ◽

Cited By ~ 1

Author(s):

Manorama Chauhan ◽

Ravindra Singh Kushwah ◽

Pavan Shrivastava ◽

Shyam Akashe

Keyword(s):

Integrated Circuits ◽

Metal Oxide ◽

Low Power ◽

High Performance ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Short Channel ◽

State Dependency ◽

Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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New Low-leakage Flip-flops with Power-gating Scheme for Ultra-low Power Systems

Information Technology Journal ◽

10.3923/itj.2011.2161.2167 ◽

2011 ◽

Vol 10 (11) ◽

pp. 2161-2167 ◽

Cited By ~ 5

Author(s):

Jianping Hu ◽

Xiaoying Yu ◽

Jindan Chen

Keyword(s):

Power Systems ◽

Low Power ◽

Power Gating ◽

Ultra Low Power ◽

Low Leakage ◽

Gating Scheme

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A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Journal of Electrical and Computer Engineering ◽

10.1155/2014/695832 ◽

2014 ◽

Vol 2014 ◽

pp. 1-10 ◽

Cited By ~ 1

Author(s):

Xiaohui Fan ◽

Yangbo Wu ◽

Hengfeng Dong ◽

Jianping Hu

Keyword(s):

Vlsi Design ◽

Leakage Power ◽

Total Power ◽

Sleep Mode ◽

Power Gating ◽

Data Retention ◽

Flip Flop ◽

Low Leakage ◽

Area Overhead ◽

Technology Process

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

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HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156495000055 ◽

1995 ◽

Vol 06 (01) ◽

pp. 163-210 ◽

Cited By ~ 3

Author(s):

STEPHEN I. LONG

Keyword(s):

Integrated Circuits ◽

Low Power ◽

Material Properties ◽

High Speed ◽

Digital Circuit ◽

Bipolar Transistor ◽

Clock Frequency ◽

Digital Integrated Circuits ◽

Heterojunction Devices ◽

Circuit Technology

The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.

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