Low-leakage and low-power implementation of high-speed 65nm logic gates

2008 ◽  
Author(s):  
Tsung-Yi Wu ◽  
Liang-Ying Lu ◽  
Cheng-Hsun Liang
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Gates ◽  
Low Leakage

Low-Leakage and Low-Power Implementation of High-Speed Logic Gates

2009 ◽  
Vol E92-C (4) ◽  
pp. 401-408
Author(s):  
Tsung-Yi WU ◽  
Liang-Ying LU
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Gates ◽  
Low Leakage

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

scholarly journals Low Power, High speed, Low leakage Floating Gate SRAM Cell using LECTOR Technique

2016 ◽  
Vol 9 (45) ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta K. Mandal ◽  
B. Shivalal Patro
Keyword(s):  
Low Power ◽  
High Speed ◽  
Floating Gate ◽  
Low Leakage ◽  
Sram Cell

scholarly journals Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder

2021 ◽  
Vol 5 (1) ◽  
pp. 1-7
Author(s):  
S. MOHAN DAS ◽  
GANESH KUMAR M ◽  
BHASKARA RAO K
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Universal Logic ◽  
Significant Saving ◽  
Low Leakage ◽  
Low Threshold ◽  
The Cost

This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.

Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits

2020 ◽  
Vol 10 (5) ◽  
pp. 696-708
Author(s):  
Rumi Rastogi ◽  
Sujata Pandey ◽  
Mridula Gupta
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Speed ◽  
Room Temperature ◽  
Leakage Power ◽  
Optimization Techniques ◽  
Power Gating ◽  
Low Leakage ◽  
Charge Recycling ◽  
A New Technique

Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

Design and Implementation of 8x8 Multiplier using 4-2 Compressor and 5-2 Compressor

2016 ◽  
Vol 5 (3) ◽  
pp. 131 ◽  
Author(s):  
K. Hari Kishore ◽  
K. Akhil ◽  
G. Viswanath ◽  
N. Pavan Kumar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Electronic Device ◽  
Logic Gates ◽  
Partial Product ◽  
Transmission Gate ◽  
Design And Implementation ◽  
Wallace Tree ◽  
Minimum Delay ◽  
Power Delay Product

In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4-2 compressors and 5-2 compressors are extensively utilized for numerical realizations. Both the compressors circuits that is the 4-2 compressor circuit and 5-2 compressor circuit internally consist of the logic gates i.e. the XOR and XNOR gates.  4-2 compressor circuit has been designed uses a brand new partial-product reduction format that consecutively reduces the utmost output new style of number needs less variety of MOSFET’s compared to Wallace Tree Multipliers. The 4-2 compressor used is created from high-speed and consists of logic gates XOR and XNOR gates and transmission gate primarily based electronic device. The regular delay and switching energy also called as power-delay product (PDP) is differentiated with the 5-2 compressor enforced with 4-2 Compressors and while not compressors, and is evidenced to own minimum delay and PDP. Simulations are performed by mistreatment Xilinx ten.1 ISE.

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