200-MHz and 400-MHz Self-Biased Temperature-Compensated Ring Oscillators in 180-nm CMOS Technology

2021 ◽  
Author(s):  
Ivan Skeledzija ◽  
Josip Mikulic ◽  
Adrijan Baric
Keyword(s):  
Cmos Technology ◽  
Ring Oscillators

High Temperature Characterization up to 450 °C of MOSFETs and basic circuits realized in a Silicon-on-Insulator (SOI) CMOS-Technology

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000227-000232
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
A. Schmidt ◽  
W. Heiermann ◽  
H. Kappert ◽  
...  
Keyword(s):  
High Temperature ◽  
Output Voltage ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Maximum Temperature ◽  
Cmos Process ◽  
Ring Oscillators ◽  
Circuit Function ◽  
Soi Cmos

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. Silicon-on-Insulator-technologies are commonly used up to 250 °C. In this work we evaluate the limit for electronic circuit function realized in thin film SOI-technologies for even higher temperatures. At Fraunhofer IMS a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metalization with excellent reliability concerning electromigration, voltage independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of NMOSFET- and PMOSFET-transistors were studied up to 450 °C. In a second step we investigated the functionality of ring oscillators, representing digital circuits, and bandgap references as examples of simple analog components. The frequency and the current consumption of ring oscillators and the output voltage of bandgap references were also characterized up to 450 °C. We found that the ring oscillator still functions at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the bandgap reference is in the specified range up to 250 °C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS-technology to its real maximum temperature limits.

scholarly journals Physically Unclonable Function using Initial Waveform of Ring Oscillators on 65nm CMOS Technology

2016 ◽  
Author(s):  
T. Tanamoto ◽  
S. Takaya ◽  
N. Sakamoto ◽  
H. Kasho ◽  
S. Yasuda ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Ring Oscillators

High-performance combined ring oscillators

2020 ◽  
Vol 39 (3) ◽  
pp. 535-550
Author(s):  
Masoud Soltani ◽  
Farzan Khatib ◽  
Seyyed Javad Seyyed Mahdavi Chabok
Keyword(s):  
Power Supply ◽  
Delay Time ◽  
Supply Voltage ◽  
Theoretical Calculations ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Ring Oscillators ◽  
Large Signal ◽  
Power Supply Voltage ◽  
Content Type

Purpose The purpose of this paper is to investigate a more robust ring oscillator. Less sensitivity to power supply variations is a target. This is important since low-quality ring oscillators could be exploited in numerous systems to reduce die costs. Design/methodology/approach The method in this work is large signal analysis. Delay time as the large signal parameter is calculated symbolically to explore dependency on a power supply voltage. Then simulations are performed to make a comparison. In this work, mathematical justifications are verified via HSPICE circuit simulator outputs, while 0.18 µm TSMC CMOS technology is exploited. Findings At least two combined configurations are presented with higher robustness. These circuits are more appropriate in noisy conditions. Both theoretical calculations and simulation results verify less sensitive oscillation against supply voltage ripples and temperature variations. Originality/value Introducing a band-switched inverter in combined configurations is contribution. In this way, three structures are presented which both show higher stability in oscillation frequency. The band switched delay time calculations are quite new and also the validity of the symbolical delay time approach is verified by circuit simulations.

High Temperature Silicon Carbide CMOS Integrated Circuits

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000115-000119 ◽  
Author(s):  
R.F. Thompson ◽  
D.T. Clark ◽  
A.E. Murphy ◽  
E.P Ramsay ◽  
D.A Smith ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Gate Dielectric ◽  
Wide Band ◽  
Cmos Technology ◽  
Ring Oscillators ◽  
Power Switching ◽  
Dielectric Performance ◽  
Floating Capacitor

The wide band-gap of Silicon Carbide makes it a material suitable for IC's [1] operating up to 450°C. The maximum operating temperature achieved will depend on the transistor technology selected, interconnect metallisation and device packaging. This paper describes transistor and circuit results achieved in SiC CMOS technology, where the major issue addressed is the gate dielectric performance. N and p-channel MOSFET structures have been demonstrated operating at temperatures up to 400°C Test circuits including simple logic cells, ring oscillators, operational amplifiers and gate drive circuits have been fabricated and the characteristics of ring oscillators are presented here. Floating capacitor structures have also been fabricated for use in future analogue and mixed signal circuits. This technology will be initially applied in applications including signal conditioning for sensors and control of SiC based power switching devices, where the high temperature capability will match that of the SiC power devices which are now becoming commercially available.

scholarly journals Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology

2017 ◽  
Vol 56 (4S) ◽  
pp. 04CF13 ◽  
Author(s):  
Tetsufumi Tanamoto ◽  
Satoshi Takaya ◽  
Nobuaki Sakamoto ◽  
Hirotsugu Kasho ◽  
Shinichi Yasuda ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Ring Oscillators

scholarly journals Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

2022 ◽  
Vol 10 (1) ◽  
pp. 732-737
Author(s):  
Prakash Sharma
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Noise Power ◽  
Ring Oscillators ◽  
Voltage Controlled Oscillator

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

2021 ◽  
Vol 16 (12) ◽  
pp. C12010
Author(s):  
L.A. Kadlubowski ◽  
P. Kmon
Keyword(s):  
Single Photon ◽  
Photon Counting ◽  
Cmos Technology ◽  
Time Of Arrival ◽  
Ring Oscillators ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Recording Channel ◽  
Simulation Results ◽  
28 Nm

Abstract The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

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