scholarly journals A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit

2018 ◽  
Vol 13 (2) ◽  
pp. 1-6
Author(s):  
Tarcisio Oliveira Moraes Junior ◽  
Raimundo Carlos Silvério Freire ◽  
Cleonilson Protásio de Souza
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Dissipation ◽  
High Efficiency ◽  
Control Circuit ◽  
Experimental Results ◽  
Cmos Process ◽  
Leakage Currents ◽  
Ultra Low Power ◽  
Rectifier Circuits

In MOSFET-transistor based rectifier circuits, leakage currents occur through both source-bulk and drain-bulk connections of their transistors causing some power dissipation decreasing their efficiency. Such a scenario is more worrying in ultra-low power circuits as those used in energy harvesting. As a solution, in this work it is proposed a control circuit of transistor bulk biasing that switches the bulk bias in an efficient way assuring adequate inversion of the source-bulk and drain-bulk junctions. The rectifier based on the proposed bulk biasing control circuit shows to be a high-efficiency one capable of reducing the leakage currents. To obtain experimental results, the circuit was fabricated in a 130 nm CMOS process and tested on a micromanipulator. The results were compared with other works where it is observed that the efficiency of our proposal reaches up to 72.5% or 5% higher that the best previous one.

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

2015 ◽  
Vol 35 (2) ◽  
pp. 421-441 ◽  
Author(s):  
Lian-xi Liu ◽  
Jun-chao Mu ◽  
Ning Ma ◽  
Wei Tu ◽  
Zhang-ming Zhu ◽  
...  
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Cmos Process ◽  
Rf Energy Harvesting ◽  
Ultra Low Power ◽  
Energy Harvesting System ◽  
Rf Energy

ULTRA-LOW POWER BOOST CONVERTER WITH CONSTANT ON-TIME-BASED MPPT FOR ENERGY HARVESTING APPLICATIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450027 ◽  
Author(s):  
MINGYANG CHEN ◽  
MENGLIAN ZHAO ◽  
QING LIU ◽  
LU WANG ◽  
XIAOBO WU
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Efficiency ◽  
Input Voltage ◽  
Boost Converter ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Voltage Range ◽  
Point Tracking ◽  
Power Point

An ultra-low power boost converter for energy harvesting applications is introduced in this brief. The idle power dissipation is reduced to 800 nW by using a novel output voltage detector (OVD) which is insensitive to temperature variation and process deviation. Furthermore, a constant on-time (COT)-based hysteretic burst mode controller with maximum power point tracking (MPPT) technique is developed to ensure high power efficiency for a wide input voltage range. After startup, the input voltage can be set as low as 30 mV. The whole system is designed and fabricated in SMIC 0.18 μm CMOS process, the end-to-end power efficiency of this converter can reach 49% at 350 mV input voltage and 65% at 750 mV input voltage.

scholarly journals Analysis and Optimization of Ultra-Low-Power Rectifier with High Efficiency for Applications in Wireless Power Transmission and Energy Harvesting

2020 ◽  
Vol 19 (1) ◽  
pp. 60-85 ◽  
Author(s):  
Raphaella Luiza Resende da Silva ◽  
Sandro Trindade Mordente Gonçalves ◽  
Christian Vollaire ◽  
Arnaud Bréard ◽  
Gláucio Lopes Ramos ◽  
...  
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
High Efficiency ◽  
Power Transmission ◽  
Wireless Power ◽  
Wireless Power Transmission ◽  
Ultra Low Power ◽  
Power Rectifier

scholarly journals A Low-Power High-Efficiency Adaptive Energy Harvesting Circuit for Broadband Piezoelectric Vibration Energy Harvester

Actuators ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 327
Author(s):  
Aicheng Zou ◽  
Zhong Liu ◽  
Xingguo Han
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Energy Harvester ◽  
High Efficiency ◽  
Control Circuit ◽  
Vibration Energy ◽  
Vibration Energy Harvester ◽  
Switch Control ◽  
Piezoelectric Vibration Energy Harvester ◽  
Piezoelectric Vibration

Existing piezoelectric vibration energy harvesting circuits require auxiliary power for the switch control module and are difficult to adapt to broadband piezoelectric vibration energy harvesters. This paper proposes a self-powered and low-power enhanced double synchronized switch harvesting (EDSSH) circuit. The proposed circuit consists of a low-power follow-up switch control circuit, reverse feedback blocking-up circuit, synchronous electric charge extraction circuit and buck-boost circuit. The EDSSH circuit can automatically adapt to the sinusoidal voltage signal with the frequency of 1 to 312.5 Hz that is output by the piezoelectric vibration energy harvester. The switch control circuit of the EDSSH circuit works intermittently for a very short time near the power extreme point and consumes a low amount of electric energy. The reverse feedback blocking-up circuit of the EDSSH circuit can keep the transmission efficiency at the optimal value. By using a charging capacitor of 1 mF, the charging efficiency of the proposed EDSSH circuit is 1.51 times that of the DSSH circuit.

Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications

2020 ◽  
Vol 29 (16) ◽  
pp. 2050261
Author(s):  
Sumalya Ghosh ◽  
Bishnu Prasad De ◽  
K. B. Maji ◽  
R. Kar ◽  
D. Mandal ◽  
...  
Keyword(s):  
Optimal Design ◽  
Low Power ◽  
Power Dissipation ◽  
Ieee 802.15.4 ◽  
Low Noise ◽  
Design Parameters ◽  
Cmos Process ◽  
Short Channel ◽  
Ultra Low Power ◽  
Cmos Lna

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4[Formula: see text]GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The designed LNA shows a gain of 15.28[Formula: see text]dB, NF of 0.376[Formula: see text]dB, the power dissipation of 936[Formula: see text][Formula: see text]W and IIP3 of [Formula: see text][Formula: see text]dBm at 2.4[Formula: see text]GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3[Formula: see text]mW[Formula: see text] and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

A 20-mV Input DC/DC Converter for Energy Harvesting Applications

2015 ◽  
Vol 24 (05) ◽  
pp. 1550070 ◽  
Author(s):  
Zheng Yang ◽  
Jingmin Wang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Management ◽  
High Efficiency ◽  
Low Power Design ◽  
Input Voltage ◽  
Voltage Source ◽  
Storage Capacitor ◽  
Cmos Process ◽  
Low Input

A low input step-up DC/DC converter and power manager in 0.18-μm CMOS process is presented. The proposed converter can work with the input voltage as low as 20 mV. The extremely low input voltage makes it suitable for energy harvesting and power management. Four logic controlled outputs provide the best voltage for various applications to accommodate low power design requirements. A low current low dropout regulator (LDO) is utilized to provide a regulated 2.2 V output for powering low power processors or other low power integrated circuit (ICs). Reserve energy on the storage capacitor CSTORE provides power when the input voltage source is unavailable, thus prolongs the life of the system and expands the application range. Extremely low quiescent current (6 μA) and high efficiency design (64%@300 μA load current) ensure the fastest possible charge times of the output reservoir capacitor. This work provides a complete power management solution for wireless sensing and data acquisition.

scholarly journals Eight-Bit Semiflash A/D Converter

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-7 ◽  
Author(s):  
D. P. Dimitrov ◽  
T. K. Vasileva
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Experimental Results ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sample And Hold ◽  
Reduced Power Consumption ◽  
Subtraction Circuit

An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

Sign in / Sign up

Export Citation Format

Share Document