scholarly journals A 59 pA/V and 62 nW Differential OTA with 0.35% THD for Biomedical Applications

2021 ◽  
Vol 16 (2) ◽  
pp. 1-11
Author(s):  
Rafael Sanchotene Silva ◽  
Luís Henrique Rodovalho ◽  
Jefferson Luiz Brum Marques ◽  
Cesar Ramos Rodrigues
Keyword(s):  
Average Power ◽  
Signal Acquisition ◽  
Operational Transconductance Amplifier ◽  
Worst Case ◽  
Fully Integrated ◽  
Transconductance Amplifier ◽  
Narrow Bandwidth ◽  
Average Power Consumption ◽  
Long Time ◽  
Electrophysiological Signal

This paper presents a novel differential pA/V Operational Transconductance Amplifier (OTA) topology. The circuit is suitable for the implementation of fully integrated operational transconductance amplifier-capacitance (OTA-C) filters with small feature size capacitors, suited for electrophysiological signal acquisition and conditioning. Unlike typical OTA-Cs, the proposed topology consists of transconductance reduction technique based on unbalanced output branches thatallow current subtraction thus enabling transconductances in the order of pA/V. The technique is demonstrated through the design of a 59pA/V transconductor, which is very suited for designing long-time-constant filters. This OTA-C achieved a worst-case 0.35% THD with just 61.7nW average power consumption, which allows its applicability to biomedical implants. Simulations were carried out with STMicroelectronics 0.13µm HCMOS9 node using Cadence’s IC design tools. Weemployed the OTA in a design of a fourth-order bandpass filter with a narrow bandwidth of 12.5–21.8Hz. Similar results to the ideal transfer function, turn the proposed OTA ideal for biosensing-based applications.

New Adders Using Hybrid Circuit Consisting of Three-Gate Single-Electron Transistors (TG-SETs) and MOSFETs

2007 ◽  
Vol 7 (11) ◽  
pp. 4120-4125
Author(s):  
Yunseop Yu ◽  
Jungbum Choi
Keyword(s):  
Field Effect Transistors ◽  
Circuit Simulation ◽  
Average Power ◽  
Single Electron ◽  
Oxide Semiconductor ◽  
Single Electron Transistors ◽  
Worst Case ◽  
Half Adder ◽  
Average Power Consumption ◽  
Electron Transistors

A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional CMOS FA with 0.35 μm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs.

scholarly journals Fully integrated high quality factor <i>G</i><sub>m</sub><i>C</i> bandpass filter stage with highly linear operational transconductance amplifier

2017 ◽  
Vol 15 ◽  
pp. 149-155 ◽  
Author(s):  
Jochen Briem ◽  
Marco Mader ◽  
Daniel Reiter ◽  
Raul Amirpour ◽  
Markus Grözing ◽  
...  
Keyword(s):  
Bandpass Filter ◽  
Process Variations ◽  
Q Factor ◽  
Operational Transconductance Amplifier ◽  
High Quality ◽  
Fully Integrated ◽  
Local Process ◽  
Transconductance Amplifier ◽  
Control Circuits ◽  
Global And Local

Abstract. This paper presents an electrical, fully integrated, high quality (Q) factor GmC bandpass filter (BPF) stage for a wireless 27 MHz direct conversion receiver for a bendable sensor system-in-foil (Briem et al., 2016). The core of the BPF with a Q factor of more than 200 is an operational transconductance amplifier (OTA) with a high linearity at an input range of up to 300 mVpp, diff. The OTA's signal-to-noise-and-distortion-ratio (SNDR) of more than 80 dB in the mentioned range is achieved by stabilizing its transconductance Gm with a respective feedback loop and a source degeneration resistors RDG. The filter stage can be tuned and is tolerant to global and local process variations due to offset and common-mode feedback (CMFB) control circuits. The results are determined by periodic steady state (PSS) simulations at more than 200 global and local process variation parameter and temperature points and corner simulations. It is expected, that the parasitic elements of the layout have no significant influence on the filter behaviour. The current consumption of the whole filter stage is less than 600 µA.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals EZ-SEP: Extended Z-SEP Routing Protocol with Hierarchical Clustering Approach for Wireless Heterogeneous Sensor Network

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1021
Author(s):  
Zhanserik Nurlan ◽  
Tamara Zhukabayeva ◽  
Mohamed Othman
Keyword(s):  
Sensor Network ◽  
Hierarchical Clustering ◽  
Routing Protocol ◽  
Routing Protocols ◽  
Cluster Head ◽  
Average Power ◽  
Base Station ◽  
Average Power Consumption ◽  
Clustering Approach ◽  
Heterogeneous Sensor Network

Wireless sensor networks (WSN) are networks of thousands of nodes installed in a defined physical environment to sense and monitor its state condition. The viability of such a network is directly dependent and limited by the power of batteries supplying the nodes of these networks, which represents a disadvantage of such a network. To improve and extend the life of WSNs, scientists around the world regularly develop various routing protocols that minimize and optimize the energy consumption of sensor network nodes. This article, introduces a new heterogeneous-aware routing protocol well known as Extended Z-SEP Routing Protocol with Hierarchical Clustering Approach for Wireless Heterogeneous Sensor Network or EZ-SEP, where the connection of nodes to a base station (BS) is done via a hybrid method, i.e., a certain amount of nodes communicate with the base station directly, while the remaining ones form a cluster to transfer data. Parameters of the field are unknown, and the field is partitioned into zones depending on the node energy. We reviewed the Z-SEP protocol concerning the election of the cluster head (CH) and its communication with BS and presented a novel extended mechanism for the selection of the CH based on remaining residual energy. In addition, EZ-SEP is weighted up using various estimation schemes such as base station repositioning, altering the field density, and variable nodes energy for comparison with the previous parent algorithm. EZ-SEP was executed and compared to routing protocols such as Z-SEP, SEP, and LEACH. The proposed algorithm performed using the MATLAB R2016b simulator. Simulation results show that our proposed extended version performs better than Z-SEP in the stability period due to an increase in the number of active nodes by 48%, in efficiency of network by the high packet delivery coefficient by 16% and optimizes the average power consumption compared to by 34.

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