scholarly journals A Switched-MOSFET Programmable Low-Voltage Filter

2004 ◽  
Vol 1 (1) ◽  
pp. 32-37
Author(s):  
Luís Cléber C. Marques ◽  
Wouter A. Serdijn
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Total Current ◽  
Sampled Data ◽  
Current Consumption ◽  
Digitally Programmable ◽  
Low Supply Voltage

This paper describes a digitally programmable low-voltage low-power analogue filter that can be used in hearing-aid circuits. The filter employs the recently introduced switched-MOSFET technique, a sampled-data technique suitable for low supply voltage operation since it avoids the conduction gap of the switches and does not need any dedicated process. The filter was implemented using the DIMES 1.6μm CMOS process and achieves 64 dB dynamic range. The total current consumption, drawn from a 2.2V supply, equals 93μA.

LOW VOLTAGE, LOW POWER CHEBYSHEV FILTER IN 0.18 μm CMOS TECHNOLOGY

2013 ◽  
Vol 22 (07) ◽  
pp. 1350053 ◽  
Author(s):  
S. REKHA ◽  
T. LAXMINIDHI
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Transconductance Amplifier ◽  
Low Pass ◽  
Unity Gain ◽  
Design Centering ◽  
Low Supply Voltage

This paper presents an active-RC continuous time filter in 0.18 μm standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 μW.

An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter

2016 ◽  
Vol 25 (06) ◽  
pp. 1650066 ◽  
Author(s):  
Pantre Kompitaya ◽  
Khanittha Kaewdang
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Cmos Technology ◽  
Low Supply Voltage

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

A 2.4 GHz Low Voltage Low Power Folded Down-Conversion Quadrature Mixer Design

2013 ◽  
Vol 760-762 ◽  
pp. 526-530
Author(s):  
Ming Li ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  
Keyword(s):  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Process ◽  
Folded Structure ◽  
Single Side ◽  
Mixer Design ◽  
Low Supply Voltage ◽  
Single Side Band ◽  
Down Conversion

This paper introduces a 2.4 GHz down-conversion quadrature mixer which applied in the Wireless Sensor Network (WSN). The mixer uses a folded structure which is modified based on the conventional Gilbert mixer. It is designed in 0.18μm RF CMOS process with a low supply voltage of 1V. The post-simulation results show that the mixer achieves a conversion gain (CG) of 9.0dB, the input 1dB compression point (IP1dB) of-7.6dBm, the third-order input intercept point (IIP3) of 2.2dBm, and the single side-band (SSB) noise figure (NF) is 13.9dB. The mixer core consumes current about 1.2mA from a 1V power supply.

An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure

2019 ◽  
Vol 28 (10) ◽  
pp. 1950172
Author(s):  
Mehdi Bandali ◽  
Alireza Hassanzadeh ◽  
Masoume Ghashghaie ◽  
Omid Hashemipour
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Current Steering ◽  
Ultra Low Power ◽  
Current Cell ◽  
Sample Rate

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[Formula: see text]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [Formula: see text]-V supply voltage with the sample rate of 140[Formula: see text]MS/s show SFDR [Formula: see text] 64.37[Formula: see text]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

A LOW-VOLTAGE LOW-POWER 10-BIT 200 MS/S PIPELINED ADC IN 90 NM CMOS

2010 ◽  
Vol 19 (02) ◽  
pp. 393-405 ◽  
Author(s):  
SAHEL ABDINIA ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Pipeline Adc ◽  
Class A ◽  
Reduction Techniques ◽  
Dynamic Comparators

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-VP-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.

scholarly journals A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC using Simultaneous Capacitor and Op-amp Sharing Technique

2021 ◽  
Author(s):  
Shylu Sam ◽  
D. Jackuline Moni ◽  
P.Sam Paul ◽  
D. Nirmal
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Effective Number ◽  
Op Amp ◽  
Integral Nonlinearity ◽  
Silicon Based ◽  
Variable G

Abstract This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp−p,diff input signal while consuming only 7.3mW power from 1.8V supply.

A COMPACT CMOS POWER-ON-RESET PULSE GENERATOR DESIGN WITH LOW-POWER AND WIDE OPERATION RANGE

2010 ◽  
Vol 19 (06) ◽  
pp. 1365-1380 ◽  
Author(s):  
SUAT U. AY
Keyword(s):  
Low Power ◽  
Pulse Generator ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Detection Capability ◽  
Voltage Range ◽  
Low Voltage Operation ◽  
Reset Pulse ◽  
Generator Design

A compact power-on-reset pulse generator (POR-PG) circuit with a low-power and low-voltage operation capability is presented. Proposed POR-PG was fabricated in 0.5 μm 2P3M CMOS process. It was determined from simulations and measurements that proposed POR-PG works supply voltage levels between 1.8 V and 3.3 V and supply voltage rise times between 100 ns and 1 ms. POR-PG has very small silicon footprint. Layout size of proposed POR-PG circuit was 120 μm × 5 μm in 0.5 μm CMOS process. Comparing with other POR-PG circuits in the literature, proposed design enjoys lowest power consumption (< 6 μW), smallest silicon footprint, widest supply voltage range, and additional features such as brown-out detection capability. These achieved by using a unique cascadable POR delay element that consumes very low-power.

scholarly journals Low-noise and low power CMOS photoreceptor using split-length MOSFET

2019 ◽  
Vol 70 (6) ◽  
pp. 480-485
Author(s):  
Jamel Nebhen ◽  
Julien Dubois ◽  
Sofiene Mansouri ◽  
Dominique Ginhac
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Vision Sensor ◽  
Current Consumption ◽  
Low Power Cmos ◽  
Design Requirements ◽  
And Performance

Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.

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