scholarly journals Application of TIVA in Design Debug

2000 ◽  
Author(s):  
Siva Kolachina ◽  
Bill Taylor ◽  
Kendall Scott Wills ◽  
Edward I. Cole
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Ring Oscillator ◽  
Induced Voltage ◽  
Thermally Induced ◽  
Isolation Techniques ◽  
Limited Success ◽  
Focussed Ion Beam ◽  
Design Debugging

Abstract Thermally-Induced Voltage Alteration (TIVA) is a relatively new technique for locating electrical defects in integrated circuits [1,2]. This paper describes a novel application of TIVA, to locate design anomalies. A newly designed integrated circuit with high and inconsistent Quiescent Power Supply Current (IDDQ) was initially diagnosed with limited success using various failsite isolation techniques. The TIVA technique was successful in accurately locating design anomalies. Results from TIVA identified a spurious ring oscillator in the design. Design modifications carried out using a focussed ion beam (FIB), verified the accuracy of the results from TIVA. This study clearly extends the use of TIVA beyond that of locating electrical defects and anomalies into the realm of design debugging.

Direct Imaging of Device Characteristics In a Focused ion Beam System

1998 ◽  
Vol 4 (S2) ◽  
pp. 652-653 ◽  
Author(s):  
A. N. Campbell ◽  
J. M. Soden
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Material Removal ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Yield Enhancement ◽  
The Past ◽  
Design Changes ◽  
Design Debugging

A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

Techniques for Localization of IC Interconnection Defects

2002 ◽  
Vol 716 ◽  
Author(s):  
Edward I. Cole
Keyword(s):  
Integrated Circuit ◽  
Constant Current ◽  
Induced Voltage ◽  
Contrast Imaging ◽  
Thermally Induced ◽  
Imaging Results ◽  
Starting Point ◽  
Site Localization ◽  
Scanning Optical Microscopy ◽  
Failure Site

AbstractThe advances in integrated circuit technology has made failure site localization extremely challenging. Charge-Induced Voltage Alteration (CIVA), Low Energy CIVA (LECIVA), Light-Induced Voltage Alteration (LIVA), Seebeck Effect Imaging (SEI) and Thermally-Induced Voltage Alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy (SEM) techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects. In addition to the techniques listed above, the Resistive Contrast Imaging (RCI) for localizing opens on metal test patterns will be described as a starting point for the “IVA” technologies.

Specific Area Planar and Cross-Sectional Lift-Out Techniques: Procedures and Novel Applications

2000 ◽  
Author(s):  
Raghaw S. Rai ◽  
Swaminathan Subramanian ◽  
Stewart Rose ◽  
James Conner ◽  
Phil Schani ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Specific Area ◽  
Cross Sectional ◽  
Site Specific ◽  
Focussed Ion Beam ◽  
Lattice Images ◽  
Novel Applications

Abstract Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

An Analytical Technique to Assess the Risk of Laser Damage to Encapsulated Integrated Circuits during Package Laser Marking

2008 ◽  
Author(s):  
Joseph Patterson ◽  
Cliff Schuring
Keyword(s):  
Integrated Circuits ◽  
Optical Beam ◽  
Laser Damage ◽  
Induced Current ◽  
Induced Voltage ◽  
Laser Marking ◽  
Thermally Induced ◽  
Analytical Technique ◽  
Optical Beam Induced Current

Abstract Damage to encapsulated integrated circuits has recently been reported due to Laser marking of the package. A method to assess the risk of such damage is presented. The method is an analytical technique using Thermally Induced Voltage Alteration (XIVA) and Optical Beam Induced Current (OBIC) imaging.

scholarly journals Die Backside FIB Preparation for Identification and Characterization of Metal Voids

1999 ◽  
Author(s):  
Ann N. Campbell ◽  
William F. Filter ◽  
Nicholas Antoniou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Milling Process ◽  
Plan View ◽  
Metal Interconnects

Abstract Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

2018 ◽  
Vol 15 (4) ◽  
pp. 163-170 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Combustion Engine ◽  
Circuit Complexity ◽  
Fold Increase ◽  
Ring Oscillator ◽  
Well Drilling ◽  
Deep Well ◽  
Air Atmosphere ◽  
And Control

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Automated End-Point Detection and Targeted Ar+ Milling of Advanced Integrated Circuit FIB TEM Specimens

2017 ◽  
Author(s):  
C.S. Bonifacio ◽  
P. Nowakowski ◽  
M.J. Campin ◽  
J.T. Harbaugh ◽  
M. Boccabella ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Specimen Preparation ◽  
Ion Milling ◽  
Transmission Electron ◽  
End Point Detection ◽  
Point Detection ◽  
Argon Ion

Abstract The sub-nanometer resolution that transmission electron microscopy (TEM) provides is critical to the development and fabrication of advanced integrated circuits. TEM specimens are usually prepared using the focused ion beam, which can cause gallium-induced artifacts and amorphization. This work presents the use of a concentrated argon ion beam for reproducible TEM specimen preparation using automatic milling termination and targeted ion milling of device features; the result is high-quality and electron-transparent specimens of less than 30 nm. Such work is relevant for semiconductor product development and failure analysis.

Systematic EFA Approach in Locating Floating Nodes in Analog Mixed Signal Devices

2011 ◽  
Author(s):  
Sagar Karki
Keyword(s):  
Integrated Circuits ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Photon Emission ◽  
Timely Manner ◽  
Critical Step ◽  
Isolation Techniques ◽  
Emission Microscopy ◽  
Digital Circuitry

Abstract With advancements in technology, it is nearly impossible to find the defects in integrated circuits without applying appropriate failure isolation techniques. Failure isolation is a critical step in identifying the physical defect on integrated circuits. This paper addresses the challenges imposed by floating node conditions on both analog and digital circuitry, and a case study for each circuit type is presented. Different approaches along with the challenges involved in isolating each case in a very timely manner are addressed. Finally, the usefulness of global isolation tools, such as PEM (Photon Emission Microscopy), FIB (Focused Ion Beam), and micro-probing, is also discussed.

Morphological and structural study of integrated circuits using XTEM and HREM

1990 ◽  
Vol 48 (4) ◽  
pp. 630-631
Author(s):  
L.M. Bharadwaj ◽  
L.M. Gantcheva ◽  
S. Simov ◽  
G. Balossier ◽  
J. Faure ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Etching Rate ◽  
Glass Plate ◽  
Region Of Interest ◽  
Specimen Preparation ◽  
Preparation Technique ◽  
Cross Sectional ◽  
Mechanical Preparation

There is increasing interest in the use of cross-sectional transmission electron microscopy (XTEM) to understand fundamental and technological problems associated with fabrication of integrated circuit (IC). This is because with XTEM it is possible to obtain exact morphological configuration and structure at atomic level of different layers and interfaces. For the study of a MOS device we used slightly modified XTEM specimen preparation technique than reported by other authors. To monitor region of interest during mechanical preparation two techniques were used as illustrated in Fig.1. First by glueing two slabs (10 × 4 mm2) of wafer each exactly identical in terms of geometrical dimension and device features and second by glueing a transparent glass plate on the top of wafer. The epoxy has higher ion beam etching rate than other materials so to obtain uniform thinning, ion beam was centered slightly away from the epoxy line . The thinned specimens were observed under Philips CM-30 electron microscope.

scholarly journals Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor

2018 ◽  
Vol 8 (8) ◽  
pp. 1331 ◽  
Author(s):  
Yasunori Takeda ◽  
Tomohito Sekine ◽  
Rei Shiwaku ◽  
Tomohide Murase ◽  
Hiroyuki Matsui ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Ring Oscillator ◽  
Driving Voltage ◽  
Organic Thin Film ◽  
Voltage Range ◽  
Type D ◽  
Polymer Semiconductor ◽  
P Type

The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

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