Laser Based Defect Localization for the Failure Analysis of Advanced Product

2006 ◽  
Author(s):  
W.Y. Cheng ◽  
T.Y. Chiu ◽  
Jon C. Lee ◽  
J.Y. Chiou
Keyword(s):  
Failure Analysis ◽  
Laser Scanning ◽  
Failure Modes ◽  
Induced Voltage ◽  
Resistance Change ◽  
Thermally Induced ◽  
Defect Localization ◽  
Defect Isolation ◽  
Site Localization ◽  
Selection Of

Abstract Emission microscopy have been used for failure analysis (FA) defect isolation. But for advanced products, the working voltage of chip is getting smaller, thus many emission spots from normal transistors will be observed, which indeed affects the judgment on the emission spots from killer defects and increases the FA difficulty. Laser scanning microscope (LSM)-based techniques have been powerful defect isolation methods for many years. In this study, Checkpoint Infrascan 200TD, a laser-based tool, is used to perform defect localization. Here, thermally induced voltage alteration and optical beam induced resistance change are used to get defect locations. The study demonstrates three FA cases with 80nm/90nm technologies; metal direct short, poly leakage, and contact high resistance are also found in these cases. It is concluded that, by the selection of control parameters, Infrascan 200TD provides several capabilities of failure site localization and can be applied to different failure modes.

Ambient Temperature Thermally Induced Voltage Alteration for Identification of Defects in Superconducting Electronics

2018 ◽  
Author(s):  
Mark W. Jenkins ◽  
Paiboon Tangyunyong ◽  
Nancy A. Missert ◽  
Alejandro A. Pimentel ◽  
Igor Vernik ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Ambient Temperature ◽  
Room Temperature ◽  
Failure Modes ◽  
State Of The Art ◽  
Cryogenic Temperatures ◽  
Induced Voltage ◽  
Thermally Induced ◽  
Analysis Techniques ◽  
Superconducting Electronics

Abstract As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.

scholarly journals Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

2020 ◽  
Vol 10 (23) ◽  
pp. 8576
Author(s):  
Han Yang ◽  
Rui Chen ◽  
Jianwei Han ◽  
Yanan Liang ◽  
Yingqi Ma ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Induced Resistance ◽  
Seebeck Effect ◽  
Comprehensive Model ◽  
Induced Voltage ◽  
Efficient Technology ◽  
Resistance Change ◽  
Scanning Velocity ◽  
Laser Stimulation ◽  
Defect Localization

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

scholarly journals Fractographic classification in metallic materials by using 3D processing and computer vision techniques

2016 ◽  
Vol 25 (43) ◽  
pp. 83-96
Author(s):  
Maria Ximena Bastidas-Rodríguez ◽  
Flavio A. Prieto-Ortíz ◽  
Édgar Espejo-Mora
Keyword(s):  
Failure Analysis ◽  
Laser Scanning ◽  
Failure Modes ◽  
Confusion Matrix ◽  
Laser Scanning Microscopy ◽  
Confocal Laser ◽  
Future Research ◽  
Support Vector ◽  
3D Vision ◽  
The Individual

Failure analysis aims at collecting information about how and why a failure is produced. The first step in this process is a visual inspection on the flaw surface that will reveal the features, marks, and texture, which characterize each type of fracture. This is generally carried out by personnel with no experience that usually lack the knowledge to do it. This paper proposes a classification method for three kinds of fractures in crystalline materials: brittle, fatigue, and ductile. The method uses 3D vision, and it is expected to support failure analysis. The features used in this work were: i) Haralick’s features and ii) the fractal dimension. These features were applied to 3D images obtained from a confocal laser scanning microscopy Zeiss LSM 700. For the classification, we evaluated two classifiers: Artificial Neural Networks and Support Vector Machine. The performance evaluation was made by extracting four marginal relations from the confusion matrix: accuracy, sensitivity, specificity, and precision, plus three evaluation methods: Receiver Operating Characteristic space, the Individual Classification Success Index, and the Jaccard’s coefficient. Despite the classification percentage obtained by an expert is better than the one obtained with the algorithm, the algorithm achieves a classification percentage near or exceeding the 60 % accuracy for the analyzed failure modes. The results presented here provide a good approach to address future research on texture analysis using 3D data.

Techniques for Localization of IC Interconnection Defects

2002 ◽  
Vol 716 ◽  
Author(s):  
Edward I. Cole
Keyword(s):  
Integrated Circuit ◽  
Constant Current ◽  
Induced Voltage ◽  
Contrast Imaging ◽  
Thermally Induced ◽  
Imaging Results ◽  
Starting Point ◽  
Site Localization ◽  
Scanning Optical Microscopy ◽  
Failure Site

AbstractThe advances in integrated circuit technology has made failure site localization extremely challenging. Charge-Induced Voltage Alteration (CIVA), Low Energy CIVA (LECIVA), Light-Induced Voltage Alteration (LIVA), Seebeck Effect Imaging (SEI) and Thermally-Induced Voltage Alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy (SEM) techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects. In addition to the techniques listed above, the Resistive Contrast Imaging (RCI) for localizing opens on metal test patterns will be described as a starting point for the “IVA” technologies.

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

2003 ◽  
Author(s):  
Seth J. Prejean ◽  
Joseph Shannon
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Easy Access ◽  
Induced Voltage ◽  
Emission Analysis ◽  
Defect Localization ◽  
Soi Devices

Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.

scholarly journals Novel Defect Detection Using Laser-Based Imaging and TIVA with a Visible Laser

2013 ◽  
Author(s):  
Mary A. Miller ◽  
Paiboon Tangyunyong ◽  
Edward I. Cole ◽  
Alejandro Pimentel ◽  
Darlene M. Udoni
Keyword(s):  
Case Studies ◽  
Laser Scanning ◽  
Laser Scanning Microscopy ◽  
Induced Voltage ◽  
Thermally Induced ◽  
First Case ◽  
Reflected Light ◽  
Visible Laser ◽  
532 Nm

Abstract This paper presents two different case studies that highlight the use of reflected light imaging in laser scanning microscopy. In the first case study, the exact location of defects in metal comb test structures were much easier to detect with reflected light imaging than with thermally-induced voltage alteration (TIVA). This case study also shows visible-wavelength TIVA defect localization using a 532-nm laser. A comparison between 532-nm TIVA and conventional 1320-nm TIVA is made to show the resolution improvement with the visible laser. In the second case study, the cause of a linear string of bit failures was localized easily with backside reflected light imaging. It is observed that the indicated sites matched the light-induced voltage alteration signals and the failing cells in the bit map. In both of the case studies, the reflected light images have proved very helpful in the localization and characterization of failing devices or test structures.

Failure Localization by Using a Novel Backside Passive Voltage Contrast Methodology

2011 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Chih-Chung Chang ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
High Resistance ◽  
Failure Modes ◽  
Good Method ◽  
Chain Structure ◽  
Active Area ◽  
Acceptance Test ◽  
Resistance Change ◽  
Analysis Technique ◽  
Voltage Contrast

Abstract Contact resistance from wafer acceptance test (WAT) data is one of the critical parameter to significantly affect fabrication process. While WAT data shows open/short fail, high resistance fail and leakage fail in contact chain structure, the first job in failure analysis (FA) field is to localize failure site. For example, High resistance failure and leakage failure sites can be localized by Infrared Ray Optical Beam Induced Resistance Change (IR-OBIRCH) detection. Most of open failure modes could be isolated by front side passive voltage contrast (PVC) technique. However, there is still a limitation to this technique while contacts are still connected to substrate in metal-1/contact/active chain structure. Active Voltage Contrast (AVC) [1, 2] is a good method to overcome this problem, but the major concern is how to mark the failure location in SEM based probing system. In this paper, we provide a novel backside passive voltage contrast method to improve the failure analysis technique. By thinning down silicon substrate to the active area, a new contact chain from active area is created. Therefore, novel backside PVC is applied to locate the failed site.

scholarly journals Failure Analysis of MEMS Using Thermally-Induced Voltage Alteration

2000 ◽  
Author(s):  
Jeremy A. Walraven ◽  
Edward I. Cole ◽  
Paiboon Tangyunyong
Keyword(s):  
Laser Scanning ◽  
Thermal Stimulus ◽  
Mems Devices ◽  
Induced Voltage ◽  
Micro Electro Mechanical Systems ◽  
New Approach ◽  
Thermally Induced ◽  
Mems Device ◽  
Heat Sinking ◽  
Significant Production

Abstract Electrical shorting in micro-electro-mechanical systems (MEMS) is a significant production and manufacturing concern. We present a new approach to localizing shorted MEMS devices using Thermally-Induced Voltage Alteration (TIVA) [1]. In TIVA, the shorted, thermally isolated MEMS device is very sensitive to thermal stimulus. The site of the MEMS short will respond as a thermocouple when heated. By monitoring the potential across the shorted MEMS device as a laser scans across the sample, an image showing the location of the thermocouple (short site) can be generated. The TIVA signal for thermally isolated MEMS devices is much higher than that observed for conventional IC interconnections. This results from the larger temperature gradients generated during laser scanning due to little or no substrate heat sinking. The capability to quickly localize shorted MEMS structures is demonstrated by several examples. Thermal modeling of heat distributions is presented and is consistent with the experimental results.

Via Chain Failure Analysis Using a Combination of E-Beam and Optical Beam Techniques

2003 ◽  
Author(s):  
Srikanth Perungulam ◽  
Albert Gleason
Keyword(s):  
Electron Microscope ◽  
Laser Scanning ◽  
Optical Beam ◽  
Induced Voltage ◽  
Scanning Microscope ◽  
Thermally Induced ◽  
Substrate Current ◽  
Voltage Contrast ◽  
Beam Technique ◽  
Scanning Electron

Abstract This paper outlines some of the optical and e-beam based techniques that can be used to isolate via chain failures. The Scanning electron microscope based techniques discussed are Passive Voltage Contrast (PVC) and Substrate Current Imaging (SCI). The optical beam technique discussed is Thermally Induced Voltage Alteration (TIVA) on the Laser Scanning Microscope. A combination of these techniques can be used to effectively analyze all types of via chain failures.

Failure Analysis of Soft Single Column Failure in Advanced Nano SRAM Device with Internal Probing Techniques

2005 ◽  
Author(s):  
Hung-Sung Lin ◽  
Wen-Tung Chang ◽  
Chia-Hsing Chao ◽  
Jesse Wang ◽  
Chang-Tan Lin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Electrical Characterization ◽  
Conductive Atomic Force Microscopy ◽  
Resistance Change ◽  
Electrical Failure ◽  
Force Microscopy ◽  
Root Cause ◽  
Atomic Force ◽  
Single Column

Abstract Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.

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