Fabrication Process, Application and Future for An Elemental Level Vertically Integratedcircuit (Elvic)

1985 ◽  
Vol 53 ◽  
Author(s):  
Tadayoshi Enomoto
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Lower Layer ◽  
Propagation Delay ◽  
Fabrication Process ◽  
Ring Oscillator ◽  
Thermal Compression ◽  
Face To Face ◽  
Integration Density ◽  
High Production

ABSTRACTA new double-layered stacked LSI fabrication process has been developed for the purpose of realizing short fabrication turn-around time, high fabrication yield and high integration density. This process, which is named “Elemental Level Vertical Integrated Circuit (ELVIC)” technology, puts 2 convenfionally made LSI chips face to face andbonds them by thermal compression. The process includes, in addition to the conventionalLSI fabrication process, vertical interconnection (VI) formation in the upper and lower LSI layers, planarization of both upper and lower layer surfaces, and inter-level connections using pressure and heat. In the experimental version, about 52,000 10 x 10 μm2 Au-on-Ti VIs were connected on a 5 x 5 mm2 chip. Each pair of mated VIs is measured for tensile strength of 4 mg force. A 2-layer, 31-stage inter- CMOS/bulk ring oscillator consisting of p-channel MOSFETs on the upppr layerand nchannel MOSFETs on the lower layer has been built. Propagation delay time per stageis 1.86 nsec at the supply voltage of 5 V. ELVIC technology can produce a variety of benefits such as high production yield, doubling integration density, latch-up free CMOS LSIs, radiation damage free LSls, multi-function, and complete mixing of bipolar, CMOS andGaAs technologies.

Fabrication process, experimental results, and application for an elemental level vertically intergrated circuit (ELVIC)

1986 ◽  
Vol 1 (4) ◽  
pp. 552-559 ◽  
Author(s):  
Tadayoshi Enomoto
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Lower Layer ◽  
Propagation Delay ◽  
Fabrication Process ◽  
Ring Oscillator ◽  
Thermal Compression ◽  
Face To Face ◽  
Integration Density ◽  
Intergrated Circuit

A new double-layered stacked LSI fabrication process has been developed for the purpose of realizing short fabrication turn-around time, high fabrication yield, and high integration density. This process, which is named “Elemental Level Vertical Integrated Circuit (ELVIC)” technology, puts two conventionally made LSI chips face to face and bonds them by thermal compression. The process includes, in addition to the conventional LSI fabrication process, vertical interconnection (VI) formation in the upper and lower LSI layers, planarization of both upper and lower layer surfaces, and inter-level connections using pressure and heat. In the experimental version, about 52 000 10X10μm2 Au-on-Ti VIs were connected on a 5×5 mm2 chip. Each pair of mated VIs was measured and had a tensile strength of 4 mg · force. A two-layer, 31-stage inter-CMOS/bulk ring oscillator consisting of p-channel MOSFETs on the upper layer and n-channel MOSFETs on the lower layer has been built. Propagation delay time per stage is 1.86 ns at the supply voltage of 5 V. ELVIC technology can produce a variety of benefits such as high production yield, doubling integration density, latchup-free CMOS LSIs, radiation-damage-free LSIs, multifunction, and complete mixing of bipolar, CMOS, and GaAs technologies.

scholarly journals Scalable High-Speed Hybrid Complementary Integrated Circuits based on Solution-Processed Organic and Inorganic Transistors

2021 ◽  
Author(s):  
Xiaozhu Wei ◽  
Shohei Kumagai ◽  
Tatsuyuki Makita ◽  
Kotaro Tsuzuku ◽  
Akifumi Yamamura ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Organic Semiconductors ◽  
High Speed ◽  
Printed Electronics ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Ring Oscillator ◽  
Suitable Material ◽  
Amorphous Metal Oxide ◽  
P Type

Abstract Printed electronics offer a cost-efficient way to realise flexible electronic devices. The combined use of p-type and n-type semiconductors would yield silicon-like integrated circuits with low power consumption and stability. However, printing complementary circuits is challenging due to a lack of suitable material systems. To counter this, we employed a hybrid system to integrate p-type organic semiconductors (OSCs) and n-type amorphous metal oxide semiconductors (MOSs). These damage-free patterned OSC- and MOS-based thin-film transistors with improved process durability allowed the fabrication of hybrid complementary circuits on flexible substrates. These inverters functioned well even after exposure to air for 5 months. A large noise margin and power gain of 38 were realised with a supply voltage as low as 7 V. Furthermore, a five-stage ring oscillator with a stage propagation delay of 1.3 µs was achieved, which is the fastest operation ever reported for printed, flexible complementary inverters.

Amorphous IGZO TFTs and Circuits on Highly Flexible and Dimensionally Stable Kovar (Ni-Fe alloy) Metal Foils

2011 ◽  
Vol 1287 ◽  
Author(s):  
Shahrukh A. Khan ◽  
Xiaoxiao Ma ◽  
Nack Bong Choi ◽  
Miltiadis Hatalis
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Supply Voltage ◽  
Flexible Substrate ◽  
Propagation Delay ◽  
Ring Oscillator ◽  
High Yield ◽  
Uniaxial Tensile ◽  
Device Integration ◽  
Substrate Annealing

ABSTRACTWe have fabricated high performance amorphous IGZO TFTs and integrated circuits on flexible kovar (Ni-Fe 42 alloy) foils. Excellent dimensional stability on kovar foils is obtained by a pre-anneal process at 800°C that limits the thermal run-out to within 100ppm. After substrate annealing, Ni-Fe 42 alloy retains high yield strength and good flexibility with the re-crystallized structure containing large isotropic grains between 20-50μm. Amorphous IGZO TFTs and circuits with a staggered, bottom-gate architecture are fabricated and tested. Non-flexed TFTs have field effect mobility of 12 cm2/V.s, threshold voltage around 2 V and sub-threshold swing of 0.6 V/decade and ON/OFF current ratio exceeding 107. Under prolonged uniaxial tensile strain upto 0.8%, TFTs exhibited minimal change in performance which augers well for use of Ni-Fe foil as flexible substrates. To demonstrate the viability of oxide-based device integration, n-type pseudo logic ring oscillator circuits are also evaluated. Sub 300 ns propagation delay is confirmed at a rail-rail supply voltage of 40 V. The results suggest that device integration on such a highly flexible substrate is amenable to roll-to-roll processing of future electronics.

Timing Characterization of a Tester Operated Integrated Circuit by Continuous and Pulsed Laser Stimulation

2010 ◽  
Author(s):  
Tuba Kiyan ◽  
Christof Brillert ◽  
Christian Boit
Keyword(s):  
Integrated Circuit ◽  
Continuous Wave ◽  
Supply Voltage ◽  
Pulsed Laser ◽  
Drain Current ◽  
Propagation Delay ◽  
Laser Stimulation ◽  
Laser Condition ◽  
Secondary Phenomenon

Abstract The scope of this work is to investigate the timing characteristics of a state of the art fully functional IC through continuous wave (CW) and pulsed laser stimulation. The propagation delay of a gate depends on the drain current of nMOS and pMOS transistors, load capacitance and supply voltage. Localized photocurrent induced by laser beam alters some of these electrical characteristics, resulting in a change in the switching time of the gate. In addition to the desired local timing influence, a global effect on the timing throughout the full scanning period occurs as secondary phenomenon that - if not taken into account properly, may mask the local signal. This effect is strong under CW laser operation and can be drastically reduced in pulsed laser condition.

Slant-Scanning and Interstice-Bridging Applied to ZMR to Improve the Quality of Recrystallized Si Films on Quartz

1986 ◽  
Vol 71 ◽  
Author(s):  
Hisashi Tomita ◽  
Shigeru Kojima ◽  
Setsuo Usui
Keyword(s):  
Standard Deviation ◽  
Supply Voltage ◽  
Feedback System ◽  
Propagation Delay ◽  
Zone Melting ◽  
Ring Oscillator ◽  
Scanning Method ◽  
Texture Generation ◽  
Average Electron ◽  
Si Films

AbstractCMOS test circuit chips have been fabricated for the purpose of evaluating Si film recrystallized on quartz wafers by using a graphite-strip heater oven equipped with a micro-computer feedback system. Two new methods have been applied to the zone-melting recrystallization technique to produce a highly uniform and grain boundary (GB) free recrystallized Si film. The slant-scanning method was used to control the GB's location in recrystallized Si film of 180μm wide stripes separated by 20μm. The intersticebridging method was used to reduce the (111) texture generation to less than 1%. The average electron mobility and the average threshold voltage for MOSFET's were 960cm2/V sec, with a standard deviation of 43cm2/V sec, and 1.38V with a standard deviation of 0.25V, respectively. For the ring oscillator, at a supply voltage of 12V, the propagation delay time was 1.7nsec per stage. The maximum response frequency was higher than IMHz for the CMOS inverters.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

scholarly journals E/D-Mode GaN Inverter on a 150-mm Si Wafer Based on p-GaN Gate E-Mode HEMT Technology

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 617
Author(s):  
Li-Fang Jia ◽  
Lian Zhang ◽  
Jin-Ping Xiao ◽  
Zhe Cheng ◽  
De-Feng Lin ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Room Temperature ◽  
Supply Voltage ◽  
High Input ◽  
Smart Power ◽  
Input Noise ◽  
Power Integrated Circuit ◽  
Different Temperatures ◽  
Device Technology ◽  
Si Wafer

AlGaN/GaN E/D-mode GaN inverters are successfully fabricated on a 150-mm Si wafer. P-GaN gate technology is applied to be compatible with the commercial E-mode GaN power device technology platform and a systematic study of E/D-mode GaN inverters has been conducted with detail. The key electrical characters have been analyzed from room temperature (RT) to 200 °C. Small variations of the inverters are observed at different temperatures. The logic swing voltage of 2.91 V and 2.89 V are observed at RT and 200 °C at a supply voltage of 3 V. Correspondingly, low/high input noise margins of 0.78 V/1.67 V and 0.68 V/1.72 V are observed at RT and 200 °C. The inverters also demonstrate small rising edge time of the output signal. The results show great potential for GaN smart power integrated circuit (IC) application.

Supply Voltage Dependence of Ring Oscillator Frequencies for Total Ionizing Dose Exposures for 7-nm Bulk FinFET Technology

2021 ◽  
pp. 1-1
Author(s):  
Yoni Xiong ◽  
Alexandra T. Feeley ◽  
Peng Fei Wang ◽  
Xun Li ◽  
En Xia Zhang ◽  
...  
Keyword(s):  
Voltage Dependence ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Total Ionizing Dose

scholarly journals ECL-Based SiC Logic Circuits for Extreme Temperatures

2015 ◽  
Vol 821-823 ◽  
pp. 910-913 ◽  
Author(s):  
Luigia Lanni ◽  
Bengt Gunnar Malm ◽  
Mikael Östling ◽  
Carl Mikael Zetterling
Keyword(s):  
Power Consumption ◽  
Oscillation Frequency ◽  
Digital Circuits ◽  
Supply Voltage ◽  
Logic Circuits ◽  
Ring Oscillator ◽  
Extreme Temperatures ◽  
Temperature Range ◽  
Stable Noise ◽  
Gate Design

Integrated digital circuits, fabricated in a bipolar SiC technology, have been successfully tested up to 600 °C. Operated with-15 V supply voltage from 27 up to 600 °C OR-NOR gates exhibit stable noise margins of about 1 or 1.5 V depending on the gate design, and increasing delay-power consumption product in the range 100 - 200 nJ. In the same temperature range an oscillation frequency of about 1 MHz is also reported for an 11-stage ring oscillator.

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