Optimization of EeLADA for Circuit Logic Defect Localization Using Defect Simulation

2016 ◽  
Author(s):  
M. Lee ◽  
B.L. Yeoh ◽  
S.H. Goh ◽  
G.F. You ◽  
Alan Tan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Digital Device ◽  
Laser Stimulation ◽  
Successful Case ◽  
Alternative Approach ◽  
Defect Localization ◽  
Multi Level ◽  
Defect Simulation

Abstract EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

Case Study: Combined Dynamic Laser Stimulation and Static Emission Microscopy Techniques Applied to Scan Test Failure on Mixed Mode Device

2012 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Philippe Rousseille
Keyword(s):  
Mixed Mode ◽  
Laser Stimulation ◽  
Scan Test ◽  
Silicon Bulk ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Test Failure

Abstract This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

Short Wavelength Probing for Fault Isolation Applications

2020 ◽  
Author(s):  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Vasanth Somasundaram ◽  
Phoa Angeline ◽  
Pey Kin Leong ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Spatial Resolution ◽  
Short Wavelength ◽  
Fault Isolation ◽  
Laser Probing ◽  
Successful Case ◽  
20 Nm

Abstract Short wavelength probing (SWP) uses wavelengths of light shorter than 1100 nm or energies higher than silicon bandgap for laser probing applications. While SWP allows a significant improvement to spatial resolution, there are aberrations to the collected laser probing waveforms which result in difficulties in signal interpretations. In this work, we assess the signals collected through SWP (785 nm) and introduce a photodiode model to explain the observations. We also present a successful case study using 785 nm for failure analysis in sub-20 nm FinFET technology.

Backside EBIRCH Defect Localization for Advanced Flip-Chip Failure Analysis

2021 ◽  
Author(s):  
Chuan Zhang ◽  
Jane Y. Li ◽  
John Aguada ◽  
Howard Marks
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Flip Chips ◽  
Defect Localization ◽  
Localization Approach

Abstract This paper introduced a novel defect localization approach by performing EBIRCH isolation from backside of flip-chips. Sample preparation and probing consideration was discussed, and then a case study was used to illustrate how the backside EBIRCH technique provides a powerful solution in capturing and root-causing subtle defects in challenging flip-chip failures.

Multi-Level Approach for High-Precision Cache Fault Isolation—Case Study: Itanium® II Processor Low Voltage Cache Yield Improvement

2004 ◽  
Author(s):  
Chia Ling Kong ◽  
Mohammed R. Islam
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Low Voltage ◽  
Circuit Simulation ◽  
Physical Structure ◽  
Fault Isolation ◽  
Embedded Memory ◽  
Yield Improvement ◽  
Multi Level

Abstract Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.

Laser Stimulation Effect on FinFET and Case Study

2015 ◽  
Author(s):  
Kyeongju Jin ◽  
Sukho Lee ◽  
Keonil Kim ◽  
Yunwoo Lee ◽  
Yojoung Kim
Keyword(s):  
Experimental Data ◽  
The Other ◽  
Laser Source ◽  
Laser Stimulation ◽  
Two Photon ◽  
Cw Laser ◽  
Defect Localization ◽  
Laser Sources ◽  
Scan Chain

Abstract In the case of conventional planar FET, Dynamic Laser Stimulation (DLS) is a very effective method to isolate marginal failure. Depending on laser sources, DLS is divided by Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). SDL uses 1320nm wavelength laser source in order to induce localized heat. On the other hand, LADA uses 1064nm wavelength laser source to generate photo carriers. But for the FinFET the effect of laser stimulation is not clear yet. This paper introduces the effect of laser stimulation on FinFET transistors based on wavelength, the so called LADA and two-photon LADA. The experimental data show changes in Vth and Idsat with different character for a single FinFET transistor. A case study further explains this laser stimulation effect via scan chain LVcc marginal failure analysis localized with 1320nm CW laser stimulation and nano-probing analysis.

Stacked Polysilicon/Metal Capacitors Failure Analysis

2005 ◽  
Author(s):  
Dat T. Nguyen ◽  
Frank Huang
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Visual Defect ◽  
Capacitor Plate ◽  
Chemical Etch ◽  
Defect Localization ◽  
Voltage Contrast

Abstract Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.

Accurate Defect Localization of Stacked Die Devices by Lock-in Thermography

2018 ◽  
Author(s):  
Ke-Ying Lin ◽  
Chih-Yi Tang ◽  
Yu Chi Wang
Keyword(s):  
Failure Analysis ◽  
Defect Modes ◽  
Defect Localization ◽  
Lock In

Abstract The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.

Failure Analysis Case Study of a 1.5 Meter Space Flex Harness

2017 ◽  
Author(s):  
Erick Kim ◽  
Kamjou Mansour ◽  
Gil Garteiz ◽  
Javeck Verdugo ◽  
Ryan Ross ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Modes ◽  
Field Of View ◽  
Area Of Interest ◽  
Air Stream ◽  
Novel Method ◽  
Temperature Controlled ◽  
Non Destructive ◽  
Failure Site

Abstract This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.

Low Temperature Fault Isolation Using Soft Defect Localization

2012 ◽  
Author(s):  
Kristopher D. Staller
Keyword(s):  
Low Temperatures ◽  
Laser Scanning ◽  
Low Cost ◽  
Fault Isolation ◽  
Laser Scanning Microscopy ◽  
Cold Temperature ◽  
Multiple Point ◽  
Defect Localization ◽  
Low Levels

Abstract Cold temperature failures are often difficult to resolve, especially those at extreme low levels (< -40°C). Momentary application of chill spray can confirm the failure mode, but is impractical during photoemission microscopy (PEM), laser scanning microscopy (LSM), and multiple point microprobing. This paper will examine relatively low-cost cold temperature systems that can hold samples at steady state extreme low temperatures and describe a case study where a cold temperature stage was combined with LSM soft defect localization (SDL) to rapidly identify the cause of a complex cold temperature failure mechanism.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

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