scholarly journals The Analysis of SEU in Nanowire FETs and Nanosheet FETs

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 863
Author(s):  
Yunjae Kim ◽  
Myounggon Kang
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Incident Angle ◽  
Three Dimensional ◽  
Design Tools ◽  
Single Event Upset ◽  
Single Event ◽  
The Difference ◽  
Aided Design

The effects of the single-event upset (SEU) generated by radiation on nanowire field-effect transistors (NW-FETs) and nanosheet (NS)-FETs were analyzed according to the incident angle and location of radiation, by using three-dimensional technology computer-aided design tools. The greatest SEU occurred when the particle was incident at 90°, whereas the least occurred at 15°. SEU was significantly affected when the particle was incident on the drain, as compared to when it was incident on the source. The NS-FETs were robust to SEU, unlike the NW-FETs. This phenomenon can be attributed to the difference in the area exposed to radiation, even if the channel widths of these devices were identical.

scholarly journals Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

2020 ◽  
Vol 10 (24) ◽  
pp. 8880
Author(s):  
Min Woo Kang ◽  
Woo Young Choi
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Gate Insulator ◽  
Radius Of Curvature ◽  
Computer Aided ◽  
Simulation Results ◽  
Tcad Simulation ◽  
Aided Design

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter

2021 ◽  
Vol 21 (8) ◽  
pp. 4252-4257
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Interface Trap ◽  
Charge Effects ◽  
Trap Charge ◽  
Interlayer Dielectric ◽  
Threshold Voltages ◽  
Propagation Delays ◽  
Aided Design

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

scholarly journals Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 282 ◽  
Author(s):  
Liang Dai ◽  
Weifeng Lü ◽  
Mi Lin
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Voltage ◽  
Metal Gate ◽  
Random Dopant Fluctuation ◽  
Computer Aided ◽  
Dual Metal ◽  
Aided Design ◽  
Random Dopant

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

2021 ◽  
Author(s):  
Fahimul Islam Sakib ◽  
Md. Azizul Hasan ◽  
Mainul Hossain
Keyword(s):  
Performance Optimization ◽  
Computer Aided Design ◽  
Single Channel ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Differential Resistance ◽  
Future Technology ◽  
Aided Design ◽  
Technology Nodes ◽  
Tcad Simulations

Abstract Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (ION ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher ION/IOFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

scholarly journals Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yejin Yang ◽  
Young-Soo Park ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Drain Current ◽  
Memory Window ◽  
Interface Trap ◽  
Electrical Characteristics ◽  
The Difference ◽  
Trap Charges

AbstractIn this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

scholarly journals Design of the universal agricultural working body and study of its parameters

2018 ◽  
Vol 224 ◽  
pp. 05006 ◽  
Author(s):  
Sergey V. Belousov ◽  
Sergey A. Pomelyayko ◽  
Vladislav V. Novikov
Keyword(s):  
Computer Aided Design ◽  
Three Dimensional ◽  
Experiment Planning ◽  
Design Tools ◽  
Computer Aided ◽  
Scientific Approach ◽  
Factors Of Influence ◽  
Working Bodies ◽  
Aided Design ◽  
Work Done

The article is devoted to the scientific approach with the help of computer-aided design tools for modeling the processes of interaction of tillage tools with soil. The article has an applied character, which is expressed in the fact that the method of computer-aided design in Mathcad using software CAD COMPASS 3D has been used. The analyses of expressions in the form of three-dimensional graphs are widely presented and their detailed review is given, which can be used to perform the improvement of the design of units that perform the main treatment of the soil with a turnover of a layer. As a result of the work done, there was obtained a combined plowshare with additional flat-cutting working bodies, there was made a matrix of experiment planning, there was obtained a graph of the dependence of the width grip of the flat-cutting razor on the speed of the arable unit. There were substantiated the factors of influence on performance as a result of using the planning of the two-factor experiment due to the orthogonal plan, there were determined the optimal settings of the operation modes of the plowshare.

Si1-yGeyor Ge1-zSnzSource/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

2013 ◽  
Vol 52 (4S) ◽  
pp. 04CC01 ◽  
Author(s):  
Geert Eneman ◽  
An De Keersgieter ◽  
Liesbeth Witters ◽  
Jerome Mitard ◽  
Benjamin Vincent ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Design Study ◽  
Computer Aided ◽  
P Type ◽  
Aided Design

scholarly journals A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 164
Author(s):  
Ke Han ◽  
Shanglin Long ◽  
Zhongliang Deng ◽  
Yannan Zhang ◽  
Jiawei Li
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Source Voltage ◽  
Effect Transistor ◽  
Supply Current ◽  
Aided Design

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance

2009 ◽  
Vol 1174 ◽  
Author(s):  
Yasaman Shadrokh ◽  
Kristel Fobelets ◽  
Enrique Velazquez-Perez
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Degrees Of Freedom ◽  
Field Effect Transistors ◽  
Switching Speed ◽  
High Drive ◽  
Gate Control ◽  
Effect Transistor ◽  
Screen Grid ◽  
Aided Design

AbstractReduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed.

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