scholarly journals Comparative Study on the “Soft Errors” Induced by Single-Event Effect and Space Electrostatic Discharge

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 802
Author(s):  
Rui Chen ◽  
Li Chen ◽  
Jianwei Han ◽  
Xuan Wang ◽  
Yanan Liang ◽  
...  
Keyword(s):  
Comparative Study ◽  
Computer Aided Design ◽  
Electrostatic Discharge ◽  
Soft Errors ◽  
Random Access ◽  
Test System ◽  
Single Event ◽  
Single Event Effect ◽  
Similarity And Difference ◽  
Aided Design

Single event effect (SEE) and space electrostatic discharge (SESD) are two important types of effects causing spacecraft anomalies. However, it is difficult to differentiate them to identify the root cause of on-orbit anomalies. This paper pioneers the comparative study of the “soft errors” induced by the SEE and SESD with a well-known static random-access memory (SRAM). The similarity and difference of the physical mechanisms between the “soft errors” induced by SEE and SESD are studied with the technology computer-aided design (TCAD) simulations. Meanwhile, the characteristics of the “soft errors” and the relation with external stimulus between SEE and SESD are further investigated with the pulsed laser SEE facility and SESD test system. The results showed that the similar appearances of “soft errors” can be generated by both SEE and SESD, while multiple-bit upset (MBU) has been observed only in SESD testing. In addition, in comparison to the random distribution of SEE sensitivity areas, the SESD sensitivity areas are in closer proximity to the power supply regions. The different symptoms in upsets can be used to identify the root causes of the spacecraft anomalies.

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Performance of Distributed Generation (DG) towards Dynamic Voltage Restorer (DVR) in Mitigating Voltage Dips

2015 ◽  
Vol 793 ◽  
pp. 3-8
Author(s):  
Melaty Amirruddin ◽  
Muhd Hafizi Idris ◽  
A.H. Hana ◽  
N.S. Noorpi ◽  
O. Mardianaliza ◽  
...  
Keyword(s):  
Distributed Generation ◽  
Computer Aided Design ◽  
Test System ◽  
Dynamic Voltage Restorer ◽  
Ground Fault ◽  
Voltage Restorer ◽  
Computer Aided ◽  
Voltage Dips ◽  
Dynamic Voltage ◽  
Aided Design

This article presents the performance of Distributed Generation (DG) towards Dynamic Voltage Restorer (DVR) in mitigating voltage dips. An investigation was conducted to explore the effect of DG with the test system and the results will be analyzed during line to ground fault with DVR contains DG and without DG. The percentages of the voltage dips that occur will be compared between all the test systems. From this analysis of voltage dips percentage, the effectiveness of the DG towards DVR in mitigating voltage dips can be obtained clearly. The simulation of the test system will be done using Power System Computer Aided Design (PSCAD) software.

scholarly journals A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1198
Author(s):  
Han Li ◽  
Chen Wang ◽  
Lin Chen ◽  
Hao Zhu ◽  
Qingqing Sun
Keyword(s):  
Computer Aided Design ◽  
Random Access ◽  
Floating Gate ◽  
Silicon On Insulator ◽  
Semiconductor Electronic ◽  
Floating Gate Memory ◽  
Retention Characteristics ◽  
Tcad Simulation ◽  
Aided Design ◽  
Physical Challenges

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

A New Test Environment Approach to SEE Detection in MOSFETs

2015 ◽  
Vol 1083 ◽  
pp. 197-201 ◽  
Author(s):  
Luis E. Seixas ◽  
M.A.G. Silveira ◽  
N.H. Medina ◽  
V.A.P. Aguiar ◽  
N. Added ◽  
...  
Keyword(s):  
Heavy Ion ◽  
Test System ◽  
Ion Beams ◽  
Geometric Factor ◽  
Single Event ◽  
Test Environment ◽  
New Approach ◽  
Single Event Effect ◽  
Pelletron Accelerator

This paper shows a comparison between two different MOSFET structures: a conventional layout (CM) and Diamond (DM - enclosed layout transistor), as tolerance to the Single Event effect - SEE. Both CMOS 0.35μm technology devices types have the same geometric factor (W/L) and during irradiation were monitored continuously to detect and acquire the SEEs applying a new approach with a PXI test system. For this work was used heavy ion beams produced at the São Paulo 8 UD Pelletron accelerator.

scholarly journals A Design of Single Event Effect Test System

2021 ◽  
Vol 1971 (1) ◽  
pp. 012016
Author(s):  
Na Yan ◽  
Kun Zhang ◽  
Peiyuan Xv ◽  
Xiaodong Zhao
Keyword(s):  
Test System ◽  
Single Event ◽  
Single Event Effect ◽  
Effect Test

Case Study—Doping Profile Analysis for 30 nm DRAM Devices Using SCM and SSRM

2015 ◽  
Author(s):  
Hsiu-Pin Chen ◽  
Jian-Shing Luo ◽  
Ching-Shan Sung ◽  
Chen-Kang Wei ◽  
Kai-Lun Chiang ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Profile Analysis ◽  
Random Access ◽  
Doping Profile ◽  
Performance Tuning ◽  
Real Case ◽  
Feature Size ◽  
Aided Design ◽  
Doping Profiles

Abstract This paper is to evaluate the doping profile analysis capability of Scanning Capacitance Microscope (SCM) and Scanning Spreading Resistance Microscope (SSRM) on 30nm Dynamic Random Access Memory (DRAM) devices and apply the SSRM technique on a real case to verify the junction depths of different doping recipes for device performance tuning. The results show SCM can be used on periphery devices in a 30nm DRAM due to they have larger feature size (>90nm). For array devices with minimum feature size (~30nm) in a 30nm DRAM, only SSRM is capable with sufficient spatial resolution and sensitivity to identify the structures and doping profiles. For the real case, SSRM analysis results clarified there is approximate 10nm difference on the junction depth between 2 different doping recipes of samples and the result is consistent with the Technology Computer Aided Design (TCAD) simulation data. In addition, both SCM and SSRM techniques showed the analysis quality does highly rely on the surface cleanness and flatness of samples.

scholarly journals A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors

Micromachines ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 256
Author(s):  
Woo Young Choi ◽  
Gyuhan Yoon ◽  
Woo Young Chung ◽  
Younghoon Cho ◽  
Seongun Shin ◽  
...  
Keyword(s):  
Prediction Model ◽  
Computer Aided Design ◽  
Dielectric Breakdown ◽  
Three Dimensional ◽  
Random Access ◽  
Reliability Prediction ◽  
Dimensional Structure ◽  
Storage Capacitor ◽  
Computer Aided ◽  
Aided Design

A full three-dimensional technology-computer-aided-design-based reliability prediction model was proposed for dynamic random-access memory (DRAM) storage capacitors. The model can be used to predict the time-dependent dielectric breakdown as well as leakage current of a state-of-the-art DRAM storage capacitor with a complex three-dimensional structure.

scholarly journals Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 952
Author(s):  
Songyi Yoo ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Retention Time ◽  
Computer Aided Design ◽  
Memory Performance ◽  
Scaling Limit ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Device ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Aided Design

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

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