scholarly journals A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1198
Author(s):  
Han Li ◽  
Chen Wang ◽  
Lin Chen ◽  
Hao Zhu ◽  
Qingqing Sun
Keyword(s):  
Computer Aided Design ◽  
Random Access ◽  
Floating Gate ◽  
Silicon On Insulator ◽  
Semiconductor Electronic ◽  
Floating Gate Memory ◽  
Retention Characteristics ◽  
Tcad Simulation ◽  
Aided Design ◽  
Physical Challenges

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

scholarly journals A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1775
Author(s):  
Jae-Min Sim ◽  
Myounggon Kang ◽  
Yun-Heub Song
Keyword(s):  
Electric Field ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Fundamental Problem ◽  
Adjacent Cell ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Fundamental Cause ◽  
Tcad Simulation ◽  
Aided Design

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

scholarly journals 3D AND-Type Stacked Array for Neuromorphic Systems

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 829
Author(s):  
Taejin Jang ◽  
Suhyeon Kim ◽  
Jeesoo Chang ◽  
Kyung Kyu Min ◽  
Sungmin Hwang ◽  
...  
Keyword(s):  
Flash Memory ◽  
Computer Aided Design ◽  
Power Level ◽  
Matrix Multiplication ◽  
Simple Program ◽  
Neuromorphic Systems ◽  
Tcad Simulation ◽  
Cell Variation ◽  
Aided Design ◽  
Implantation Method

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

Performance of Direct Tunneling Floating Gate Memory with Medium-κ Dielectrics for Embedded-Random-Access Memory Applications

2006 ◽  
Vol 45 (4B) ◽  
pp. 3170-3175
Author(s):  
Bogdan Govoreanu ◽  
Robin Degraeve ◽  
Thomas Kauerauf ◽  
Wim Magnus ◽  
Dirk Wellekens ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Floating Gate ◽  
Access Memory ◽  
Direct Tunneling ◽  
Floating Gate Memory ◽  
Memory Applications

scholarly journals Modeling Nanoscale III–V Channel MOSFETs with the Self-Consistent Multi-Valley/Multi-Subband Monte Carlo Approach

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2472
Author(s):  
Enrico Caruso ◽  
David Esseni ◽  
Elena Gnani ◽  
Daniel Lizzit ◽  
Pierpaolo Palestri ◽  
...  
Keyword(s):  
Monte Carlo ◽  
Computer Aided Design ◽  
Model Verification ◽  
Boltzmann Transport ◽  
Drift Diffusion Model ◽  
Transport Direction ◽  
Nanoscale Mosfets ◽  
Tcad Simulation ◽  
Aided Design ◽  
Non Equilibrium Green’S Function

We describe the multi-valley/multi-subband Monte Carlo (MV–MSMC) approach to model nanoscale MOSFETs featuring III–V semiconductors as channel material. This approach describes carrier quantization normal to the channel direction, solving the Schrödinger equation while off-equilibrium transport is captured by the multi-valley/multi-subband Boltzmann transport equation. In this paper, we outline a methodology to include quantum effects along the transport direction (namely, source-to-drain tunneling) and provide model verification by comparison with Non-Equilibrium Green’s Function results for nanoscale MOSFETs with InAs and InGaAs channels. It is then shown how to use the MV–MSMC to calibrate a Technology Computer Aided Design (TCAD) simulation deck based on the drift–diffusion model that allows much faster simulations and opens the doors to variability studies in III–V channel MOSFETs.

scholarly journals Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1422
Author(s):  
Ki-Yeong Kim ◽  
Joo-Seok Noh ◽  
Tae-Young Yoon ◽  
Jang-Hyun Kim
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Buffer Layers ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Insulated Gate Bipolar Transistor ◽  
Computer Aided ◽  
Long Time ◽  
Tcad Simulation ◽  
Aided Design

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

TCAD simulation of a single Monolithic Active Pixel Sensors based on High Voltage CMOS technology

MRS Advances ◽  
2018 ◽  
Vol 3 (51) ◽  
pp. 3053-3059
Author(s):  
Tuan A. Bui ◽  
Geoffrey K. Reeves ◽  
Patrick W. Leech ◽  
Anthony S. Holland ◽  
Geoffrey Taylor
Keyword(s):  
High Voltage ◽  
Computer Aided Design ◽  
Cmos Technology ◽  
Active Pixel Sensors ◽  
Readout Circuits ◽  
Active Pixel ◽  
Pixel Sensors ◽  
Tcad Simulation ◽  
Response Output ◽  
Aided Design

ABSTRACTA model of a High Voltage CMOS (HV-CMOS) Monolithic Active Pixel Sensor (MAPS) has been modelled using Technology Computer Aided Design (TCAD). The model has incorporated both the active region and the on-pixel readout circuits which were comprised of a source follower amplifier and an integrated charge amplifier. The simulation has examined the electrical characteristics and response output of a HV-CMOS MAPS sensor using typical dimensions, levels of doping in the structural layers and bias conditions for this sensor. The performance of two alternate designs of amplifier have been examined as a function of the operating parameters. The response of the sensor to the incidence of Minimum Ionizing Particles (MIPs) at different energies has been included in the model.

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