scholarly journals Modeling Nanoscale III–V Channel MOSFETs with the Self-Consistent Multi-Valley/Multi-Subband Monte Carlo Approach

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2472
Author(s):  
Enrico Caruso ◽  
David Esseni ◽  
Elena Gnani ◽  
Daniel Lizzit ◽  
Pierpaolo Palestri ◽  
...  

We describe the multi-valley/multi-subband Monte Carlo (MV–MSMC) approach to model nanoscale MOSFETs featuring III–V semiconductors as channel material. This approach describes carrier quantization normal to the channel direction, solving the Schrödinger equation while off-equilibrium transport is captured by the multi-valley/multi-subband Boltzmann transport equation. In this paper, we outline a methodology to include quantum effects along the transport direction (namely, source-to-drain tunneling) and provide model verification by comparison with Non-Equilibrium Green’s Function results for nanoscale MOSFETs with InAs and InGaAs channels. It is then shown how to use the MV–MSMC to calibrate a Technology Computer Aided Design (TCAD) simulation deck based on the drift–diffusion model that allows much faster simulations and opens the doors to variability studies in III–V channel MOSFETs.

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1775
Author(s):  
Jae-Min Sim ◽  
Myounggon Kang ◽  
Yun-Heub Song

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.


2013 ◽  
Vol 61 (1) ◽  
pp. 161-171 ◽  
Author(s):  
D.B. Tefelski ◽  
T. Piotrowski ◽  
A. Polański ◽  
J. Skubalski ◽  
V. Blideanu

Abstract The process of design of building composites, like concrete is a complex one and involves many aspects like physical and mechanical properties, durability, shielding efficiency, costs of production and dismantlement etc. There are plenty of parameters to optimize and computer tools can help to choose the best solution. A computer aided design plays an important role nowadays. It becomes more accurate, faster and cheaper, so laboratories often apply computer simulation methods prior to field testing. In case of nuclear engineering, the radiation shielding problems are of much importance, because safety of such facilities is a key point. In this article the most effective methods for neutron shielding studies based on Monte-Carlo simulations of neutron transport and nuclide activation studies in concrete are presented. Two codes: MCNPX and CINDER’90 are extensively used to compare the shielding efficiency of commonly used concretes and to study the influence of concentration of B, Ba and Fe elements on shielding efficiency


Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.


Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 829
Author(s):  
Taejin Jang ◽  
Suhyeon Kim ◽  
Jeesoo Chang ◽  
Kyung Kyu Min ◽  
Sungmin Hwang ◽  
...  

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.


Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1422
Author(s):  
Ki-Yeong Kim ◽  
Joo-Seok Noh ◽  
Tae-Young Yoon ◽  
Jang-Hyun Kim

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.


Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1198
Author(s):  
Han Li ◽  
Chen Wang ◽  
Lin Chen ◽  
Hao Zhu ◽  
Qingqing Sun

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.


MRS Advances ◽  
2018 ◽  
Vol 3 (51) ◽  
pp. 3053-3059
Author(s):  
Tuan A. Bui ◽  
Geoffrey K. Reeves ◽  
Patrick W. Leech ◽  
Anthony S. Holland ◽  
Geoffrey Taylor

ABSTRACTA model of a High Voltage CMOS (HV-CMOS) Monolithic Active Pixel Sensor (MAPS) has been modelled using Technology Computer Aided Design (TCAD). The model has incorporated both the active region and the on-pixel readout circuits which were comprised of a source follower amplifier and an integrated charge amplifier. The simulation has examined the electrical characteristics and response output of a HV-CMOS MAPS sensor using typical dimensions, levels of doping in the structural layers and bias conditions for this sensor. The performance of two alternate designs of amplifier have been examined as a function of the operating parameters. The response of the sensor to the incidence of Minimum Ionizing Particles (MIPs) at different energies has been included in the model.


Polymers ◽  
2019 ◽  
Vol 11 (7) ◽  
pp. 1158
Author(s):  
Liu ◽  
Guessasma ◽  
Zhu ◽  
Zhang

This study aims at reporting a strategy of designing cellular materials based on Voronoi–Monte Carlo approach for additive manufacturing. The approach is implemented to produce a fully connected cellular structure in the design space without producing material discontinuity. The main characteristics of the cellular structure, such as the density and the cell size, are controlled by means of two generation parameters, namely the number of seed points and the relaxation time. The generated cellular structures representing various designs of generated cellular wrenches are converted into surface tessellations and manufactured using stereolithography. Bending experiments are performed up to the rupture point and main attributes representing the performance of the SL-based cellular wrenches are studied with respect to the generation parameters. The results show only slight difference between CAD (Computer-Aided Design) models of the design and the real printed parts. The number of seed points is found to control the main feature of the wrench performance whereas the relaxation time is found to have a secondary effect.


Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 291
Author(s):  
Tae-Hyeon Kim ◽  
Won-Ho Jang ◽  
Jun-Hyeok Yim ◽  
Ho-Young Cha

In this study, we proposed a rectifying drain electrode that was embedded in a p-GaN gate AlGaN/GaN heterojunction field-effect transistor to achieve the unidirectional switching characteristics, without the need for a separate reverse blocking device or an additional process step. The rectifying drain electrode was implemented while using an embedded p-GaN gating electrode that was placed in front of the ohmic drain electrode. The embedded p-GaN gating electrode and the ohmic drain electrode are electrically shorted to each other. The concept was validated by technology computer aided design (TCAD) simulation along with an equivalent circuit, and the proposed device was demonstrated experimentally. The fabricated device exhibited the unidirectional characteristics successfully, with a threshold voltage of ~2 V, a maximum current density of ~100 mA/mm, and a forward drain turn-on voltage of ~2 V.


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