scholarly journals Efficient Implementation on Low-Cost SoC-FPGAs of TLSv1.2 Protocol with ECC_AES Support for Secure IoT Coordinators

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1238 ◽  
Author(s):  
Ahmed Mohamed Bellemou ◽  
Antonio García ◽  
Encarnación Castillo ◽  
Nadjia Benblidia ◽  
Mohamed Anane ◽  
...  
Keyword(s):  
Elliptic Curve ◽  
High Speed ◽  
High Performance ◽  
Performance Enhancement ◽  
Low Cost ◽  
Research Field ◽  
Transport Layer ◽  
Limited Area ◽  
Secret Key ◽  
Elliptic Curve Cryptosystems

Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem. The integration of the ARM processor enables to exploit the possibility of embedded Linux features for high system flexibility. As a result, the proposed ECC accelerator requires limited area, with only 3395 LUTs on the Zynq device used to perform high-speed, 233-bit ECSMs in 413 µs, with a 50 MHz clock. Moreover, the generation of a 384-bit TLS handshake secret key between client and server coordinators requires 67.5 ms on a low cost Zynq 7Z007S device.

scholarly journals Towards a Glass New World: The Role of Ion-Exchange in Modern Technology

2021 ◽  
Vol 11 (10) ◽  
pp. 4610
Author(s):  
Simone Berneschi ◽  
Giancarlo C. Righini ◽  
Stefano Pelli
Keyword(s):  
Ion Exchange ◽  
Communication Networks ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Modern Technology ◽  
Historical Background ◽  
Wide Range ◽  
Happy Marriage

Glasses, in their different forms and compositions, have special properties that are not found in other materials. The combination of transparency and hardness at room temperature, combined with a suitable mechanical strength and excellent chemical durability, makes this material indispensable for many applications in different technological fields (as, for instance, the optical fibres which constitute the physical carrier for high-speed communication networks as well as the transducer for a wide range of high-performance sensors). For its part, ion-exchange from molten salts is a well-established, low-cost technology capable of modifying the chemical-physical properties of glass. The synergy between ion-exchange and glass has always been a happy marriage, from its ancient historical background for the realisation of wonderful artefacts, to the discovery of novel and fascinating solutions for modern technology (e.g., integrated optics). Getting inspiration from some hot topics related to the application context of this technique, the goal of this critical review is to show how ion-exchange in glass, far from being an obsolete process, can still have an important impact in everyday life, both at a merely commercial level as well as at that of frontier research.

scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

scholarly journals A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

2021 ◽  
Vol 2021 ◽  
pp. 1-8
Author(s):  
Yong Xiao ◽  
Weibin Lin ◽  
Yun Zhao ◽  
Chao Cui ◽  
Ziwen Cai
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Speed ◽  
High Performance ◽  
Prime Field ◽  
Practical Applications ◽  
Cell Library ◽  
Cryptographic Algorithm ◽  
Human Operators ◽  
Key Length

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

Mechanical and Optimization Analyses for Novel Wound Composite Axial Impeller

2009 ◽  
Author(s):  
Jifeng Wang ◽  
Qubo Li ◽  
Norbert Mu¨ller
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Three Dimensional ◽  
Von Mises Stress ◽  
Loading Conditions ◽  
Element Analysis ◽  
Wound Composite

A mechanical and optimal analyses procedure is developed to assess the stresses and deformations of Novel Wound Composite Axial-Impeller under loading conditions particular to centrifuge. This procedure is based on an analytical method and Finite Element Analysis (FEA, commercial software ANSYS) results. A low-cost, light-weight, high-performance, composite turbomachinery impeller from differently designed patterns will be evaluated. Such impellers can economically enable refrigeration plants using water as a refrigerant (R718). To create different complex patterns of impellers, MATLAB is used for creating the geometry of impellers, and CAD software UG is used to build three-dimensional impeller models. Available loading conditions are: radial body force due to high speed rotation about the cylindrical axis and fluid forces on each blade. Two-dimensional plane stress and three-dimensional stress finite element analysis are carried out using ANSYS to validate these analytical mechanical equations. The von Mises stress is investigated, and maximum stress and Tsai-Wu failure criteria are applied for composite material failure, and they generally show good agreement.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

2019 ◽  
Vol 28 (09) ◽  
pp. 1950149
Author(s):  
Bahram Rashidi ◽  
Mohammad Abedini
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Path Delay ◽  
Point Multiplication ◽  
Low Area ◽  
Elliptic Curve Cryptosystems ◽  
Edwards Curves ◽  
Special Cases ◽  
Field Multiplication

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

scholarly journals Charge-Transporting-Layer-Free, Vacuum-Free, All-Inorganic CsPbIBr2 Perovskite Solar Cells Via Dipoles-Adjusted Interface

Nanomaterials ◽  
2020 ◽  
Vol 10 (7) ◽  
pp. 1324
Author(s):  
Wentao Zhang ◽  
Zeyulin Zhang ◽  
Qubo Jiang ◽  
Ziming Wei ◽  
Yuting Zhang ◽  
...  
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Perovskite Solar Cells ◽  
Open Circuit ◽  
Research Field ◽  
Carbon Paste ◽  
Inorganic Perovskite ◽  
Electron Transporting Layer ◽  
Hole Transporting ◽  
Halide Perovskite

The inorganic perovskite has a better stability than the hybrid halide perovskite, and at the same time it has the potential to achieve an excellent photoelectric performance as the organic-inorganic hybrid halide perovskite. Thus, the pursuit of a low-cost and high-performance inorganic perovskite solar cell (PSC) is becoming the research hot point in the research field of perovskite devices. In setting out to build vacuum-free and carbon-based all-inorganic PSCs with the traits of simple fabrication and low cost, we propose the ones with a simplified vertical structure of FTO/CsPbIBr2/carbon upon interfacial modification with PEI species. In this structure, both the electron-transporting-layer and hole-transporting-layer are abandoned, and the noble metal is also replaced by the carbon paste. At the same time, FTO is modified by PEI, which brings dipoles to decrease the work function of FTO. Through our measurements, the carrier recombination has been partially suppressed, and the performance of champion PSCs has far exceeded the control devices without PEI modification, which yields a power conversion efficiency of 4.9% with an open circuit voltage of 0.9 V and a fill factor of 50.4%. Our work contributes significantly to give an available method to explore charge-transporting-layer-free, low-cost, and high-performance PSCs.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki
Keyword(s):  
High Speed ◽  
High Performance ◽  
Random Number ◽  
Low Cost ◽  
Random Number Generator ◽  
Magnetic Tunnel Junction ◽  
Random Number Generation ◽  
Cmos Technology ◽  
Random Numbers ◽  
Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

scholarly journals III–V Nanowires: Synthesis, Property Manipulations, and Device Applications

2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Ming Fang ◽  
Ning Han ◽  
Fengyun Wang ◽  
Zai-xing Yang ◽  
SenPo Yip ◽  
...  
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Volume Ratio ◽  
Chemical Vapor ◽  
Cost Effective ◽  
Research Field ◽  
Synthesis Methods ◽  
Comprehensive Overview ◽  
Device Applications ◽  
Property Control

III–V semiconductor nanowire (NW) materials possess a combination of fascinating properties, including their tunable direct bandgap, high carrier mobility, excellent mechanical flexibility, and extraordinarily large surface-to-volume ratio, making them superior candidates for next generation electronics, photonics, and sensors, even possibly on flexible substrates. Understanding the synthesis, property manipulation, and device integration of these III–V NW materials is therefore crucial for their practical implementations. In this review, we present a comprehensive overview of the recent development in III–V NWs with the focus on their cost-effective synthesis, corresponding property control, and the relevant low-operating-power device applications. We will first introduce the synthesis methods and growth mechanisms of III–V NWs, emphasizing the low-cost solid-source chemical vapor deposition (SSCVD) technique, and then discuss the physical properties of III–V NWs with special attention on their dependences on several typical factors including the choice of catalysts, NW diameters, surface roughness, and surface decorations. After that, we present several different examples in the area of high-performance photovoltaics and low-power electronic circuit prototypes to further demonstrate the potential applications of these NW materials. Towards the end, we also make some remarks on the progress made and challenges remaining in the III–V NW research field.

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