scholarly journals A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 199 ◽  
Author(s):  
Peiyuan Wan ◽  
Limei Su ◽  
Hongda Zhang ◽  
Zhijie Chen

An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.


Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 910
Author(s):  
Hanbo Jia ◽  
Xuan Guo ◽  
Danyu Wu ◽  
Lei Zhou ◽  
Jian Luan ◽  
...  

This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective sampling rate of ADC but the dynamic performance of TI-ADC system is seriously degraded by offset, gain, and timing mismatches among the channels. Timing mismatch is the most challenging barrier among these mismatches due to the difficulty and complexity of its detection and correction. An automatic wideband timing mismatch detection algorithm is proposed for achieving a wide frequency range of timing mismatch detection without complex calculations. By adopting the proposed mismatch-free variable delay line (VDL), the full-scale traversal timing mismatch correction accomplishes an accurate result without missing codes. Measurement results show that the spurious free dynamic range (SFDR) of the prototype ADC is improved from 55.2 dB to 72.8 dB after calibration at 2.4 GS/s with a 141 MHz input signal. It can achieve an SFDR above 60 dB across the entire first Nyquist band based on the timing mismatch calibration and retiming technology. The prototype ADC chip occupies an area of 3 mm × 3 mm and it consumes 420 mW from a 1.8 V supply.


2014 ◽  
Vol 602-605 ◽  
pp. 2744-2747
Author(s):  
Ting Li ◽  
Yong Zhang ◽  
Yan Wang ◽  
Lu Liu ◽  
Xu Wang

In this paper, a 16 bit 250MSPS pipelined ADC is presented. To alleviate noise induced by mismatching of the MDAC sampling network and comparator sampling network, scaling network structure is applied; to implement high-speed sampling, a high-efficient front-end circuit structure is presented; to further improve the sampling rate, a double duty cycle clock circuit is presented; to improve the linearity of the ADC, the sample and hold circuit is removed and the improved clock controlled boost circuit is used. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 0.18um CMOS process.


2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.


2013 ◽  
Vol 22 (04) ◽  
pp. 1350017 ◽  
Author(s):  
GUANZHONG HUANG ◽  
PINGFEN LIN

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.


Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3486
Author(s):  
Jae-Hun Lee ◽  
Dasom Park ◽  
Woojin Cho ◽  
Huu Phan ◽  
Cong Nguyen ◽  
...  

Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.


2006 ◽  
Vol 15 (05) ◽  
pp. 701-717 ◽  
Author(s):  
HSIAO WEI SU ◽  
YICHUANG SUN

A high-frequency highly linear tunable CMOS multiple-output operational transconductance amplifier (MO-OTA) for fully balanced current-mode OTA and capacitor (OTA-C) filters is presented. The MO-OTA is based on the cross-coupled pairs at the input and provides two pairs of differential outputs. A simple common-mode feedback (CMFB) circuit to stabilize the DC output levels of the MO-OTA is also proposed and two such CMFB circuits are used by the MO-OTA. The proposed MO-OTA is suitable for relatively low voltage (2.5 V) applications as its circuit has only two MOS transistors between the supply and ground rails. Simulated in a TSMC 0.25 μm CMOS process using PSpice, the MO-OTA has at least ± 0.3 V linear differential input signal swing with a single 2.5 V power supply and operates up to 1 GHz frequency. The MO-OTA has a THD less than -46 dB for a differential input voltage of 0.9 Vp-p at 10 MHz, dynamic range (DR) at THD = -46 dB is over 50 dB, and power consumption (with the common-mode feedback circuit) is below 8 mW for the whole tuning range. A fully balanced multiple loop feedback current-mode OTA-C filter example using the proposed MO-OTA is presented. This example also shows that the current-mode follow-the-leader-feedback (FLF) structure can achieve good performances for OTA-C filter design.


2018 ◽  
Vol 27 (08) ◽  
pp. 1850130 ◽  
Author(s):  
Saeed Naghavi ◽  
Mojde Nematzade ◽  
Niloofar Sharifi ◽  
Tohid Moradi Khanshan ◽  
Adib Abrishamifar ◽  
...  

This paper introduces a new technique to design an analog MOS switch to be used in sampled-data circuits. In any sampled-data system, the accuracy of the sampling switch is a critical parameter to determine the overall performance of the system. To satisfy accuracy requirements of the switch, a novel technique to reduce channel charge injection error is proposed. The proposed switch has a very simple structure and it uses a small area of the chip. Also, it has a low on-resistance and its variation over the input signal range is acceptable. In order to evaluate the performance of the proposed switch, simulations are done in a 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results show that the sampling errors produced by the channel charge injection is eliminated through a cancellation technique using an auxiliary transistor. The output error charge due to charge injection over a wide range of the input signal variation is very low (less than 1.45[Formula: see text]fC). Also, simulation results show that the proposed switch achieves signal-to-noise plus distortion ratio (SNDR) of 85.05[Formula: see text]dB, effective number of bits (ENOB) of 13.83, total harmonic distortion (THD) of [Formula: see text]87.23[Formula: see text]dB and spurious-free dynamic range (SFDR) of 88.14[Formula: see text]dB for a 1[Formula: see text]MHz sinusoidal input of 800[Formula: see text]mV peak-to-peak amplitude at 50[Formula: see text]MHz sampling rate with a 1.8[Formula: see text]V supply voltage.


2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Nabihah Ahmad ◽  
Rezaul Hasan

A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.


2010 ◽  
Vol 19 (02) ◽  
pp. 393-405 ◽  
Author(s):  
SAHEL ABDINIA ◽  
MOHAMMAD YAVARI

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-VP-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.


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