scholarly journals Image Processor and RISC MCU Embedded Single Chip Fingerprint Sensor

2020 ◽  
Vol 9 (4) ◽  
pp. 51
Author(s):  
Seungmin Jung
Keyword(s):  
Processing Time ◽  
Gabor Filter ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Single Chip ◽  
Fingerprint Image ◽  
Chip Area ◽  
Gate Count ◽  
Pixel Array ◽  
Fingerprint Sensor

In this paper, we propose a single chip fingerprint sensor with the algorithm processor and 16-bit MCU. The algorithm processor is a logic circuit that implements the GABOR filter and the THINNING step, which occupies 80% of the fingerprint image processing time. The rest of the algorithm is processed by embedded 16-bit MCU with small circuit volume, so all steps of the algorithm can be processed on the single chip without an external CPU. The capacitive sensing circuit was designed by applying the parasitic-insensitive integrator with the variable clock generator. The function was verified by Cadence Spectre for a 1-pixel sensor scheme and RTL and post simulation for digital blocks synthesized by Synopsys Design Compiler in 180n 2-poly 6-metal CMOS (complementary metal–oxide–semiconductor) process. The layout is done by automatic P&R for the full chip in a 96 × 96 pixel array. The chip area is 5010 μm × 5710 μm (28.61 mm2) and the gate count is 2,866,700. The result is compared with a conventional one. The proposed scheme can reduce the processing time by 57%.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals Novel Low-Complexity and Low-Power Flip-Flop Design

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 783
Author(s):  
Jin-Fa Lin ◽  
Zheng-Jie Hong ◽  
Chang-Ming Tsai ◽  
Bo-Cheng Wu ◽  
Shao-Wei Yu
Keyword(s):  
Low Power ◽  
Average Power ◽  
Circuit Complexity ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
System Level ◽  
Flip Flop ◽  
Chip Area

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

Design of Efficient Reversible BCD Adder–Subtractor Architecture and Its Optimization Using Carry Skip Logic

2016 ◽  
Vol 25 (07) ◽  
pp. 1650076 ◽  
Author(s):  
Praveena Murugesan ◽  
Thanushkodi Keppanagounder ◽  
Vijeyakumar Natarajan
Keyword(s):  
Critical Role ◽  
Optical Computing ◽  
Complementary Metal Oxide Semiconductor ◽  
Deep Submicron ◽  
Reversible Logic ◽  
Oxide Semiconductor ◽  
Single Digit ◽  
Gate Count ◽  
Ripple Carry Adder ◽  
Novel Design

In the present era, reversible logic designs play a very critical role in nanotechnology, low power complementary metal-oxide semiconductor (CMOS) designs, optical computing and, especially, in quantum computing. High power dissipation and leakage current in deep submicron technologies is a severe threat in applications created today. As a consequence, design of datapath elements in reversible logic has gained much importance. In this study, a novel design of binary coded decimal (BCD) adder/subtractor in reversible logic has been proposed. As a further optimization of the proposed reversible decimal design, carry skip (CSK) logic is used for reversible ripple carry adder stages. This reduces delay but at the expense of little hardware. The proposed BCD adder/subtractor and its optimized version are designed using structural VHDL and simulated using ModelSim 6.3f. Performance analysis reveals that the proposed BCD design demonstrates reductions in gate count, garbage outputs and constant inputs of 30.5%, 46% and 28%, respectively, and its optimized version exhibits 19.4%, 32.4% and 16% reductions in gate count, garbage outputs and constant inputs compared to the design in Ref. 14 [V. Rajmohan, V. Renganathan and M. Rajmohan, A novel reversible design of unified single digit BCD adder–subtractor, Int. J. Comput. Theor. Eng. 3 (2011) 697–700].

scholarly journals PENCOCOKAN GAMBAR SIDIK JARI DENGAN KAMERA HANDPHONE MENGGUNAKAN METODE RANSAC DAN TRANSFORMASI AFFINE BERBASIS ANDROID

Compiler ◽  
2017 ◽  
Vol 6 (1) ◽  
Author(s):  
Haruno Sajati ◽  
Dwi Nughraheny ◽  
Nova Adi Suwarso
Keyword(s):  
Image Processing ◽  
Gabor Filter ◽  
Histogram Equalization ◽  
Fingerprint Recognition ◽  
Android Application ◽  
Fingerprint Image ◽  
Android Os ◽  
Support Tools ◽  
Fingerprint Pattern ◽  
Fingerprint Sensor

Fingerprints occur due to stroke differences. These stroke differences have occurred at a time when humans are still fetal form. A normal fingerprint pattern is formed of lines and spaces. These lines are called ridges whereas the spaces between these lines are called valleys. To make an introduction to the fingerprint image requires a variety of support tools. Starting from a fingerprint machine, a smartphone that has a fingerprint sensor and much more. In this research, the acquisition of image is done by grayscaling, histogram equalization, gabor filter, binary, thinning, 8 neighbors, matching.The result of making android application with the method that has been described to show unfavorable results seen from the calculation of the accuracy of 63%. Based on testing the specs android OS devices, this application can run on android with OS 4.4.2 specification kitkat.Fingerprints occur due to stroke differences. These stroke differences have occurred at a time when humans are still fetal form. A normal fingerprint pattern is formed of lines and spaces. These lines are called ridges whereas the spaces between these lines are called valleys. To make an introduction to the fingerprint image requires a variety of support tools. Starting from a fingerprint machine, a smartphone that has a fingerprint sensor and much more. In this research, the acquisition of image is done by grayscaling, histogram equalization, gabor filter, binary, thinning, 8 neighbors, matching.The result of making android application with the method that has been described to show unfavorable results seen from the calculation of the accuracy of 63%. Based on testing the specs android OS devices, this application can run on android with OS 4.4.2 specification kitkat. Keywords : OCR Fingerprint, Fingerprint recognition, Minutiae based matching, Fingerprint image processing.

High power density SiGe millimeter-wave power amplifiers

2011 ◽  
Vol 3 (6) ◽  
pp. 615-620
Author(s):  
Thomas J. Farmer ◽  
Ali Darwish ◽  
Benjamin Huebschman ◽  
Edward Viveiros ◽  
Mona E. Zaghloul
Keyword(s):  
Power Density ◽  
Millimeter Wave ◽  
High Power ◽  
Silicon Germanium ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Two Stage ◽  
Chip Area ◽  
Power Added Efficiency

This paper presents measured results for two-stage and three-stage high-voltage/high-power (HiVP) amplifiers implemented in a commercial 0.12 μm silicon germanium (SiGe) heterojunction bipolar transistor (HBT) bipolar Complementary Metal Oxide Semiconductor (BiCMOS) process at millimeter wave. The HiVP configuration provides a new tool for millimeter-wave silicon designers to achieve large output voltage swings, high output power density, customizable bias, and a way to minimize, if not eliminate, matching circuitry at millimeter-wave frequencies. The two-stage amplifier has achieved a PSAT = 5.41 dBm with a power added efficiency (PAE) of 8.06% at center frequency 30 GHz. The three-stage amplifier has achieved a PSAT = 8.85 dBm with a PAE of 11.35% with a total chip area of 0.068 mm2 at center frequency 30 GHz. Simulation, layout, fabrication, and measurement results are presented in this paper.

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