Overview of High Performance Packaging Materials

1990 ◽  
Vol 203 ◽  
Author(s):  
Barry C. Johnson
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Building Blocks ◽  
Electrical Performance ◽  
Electronic Systems ◽  
Circuit Performance ◽  
Signal Velocity ◽  
Semiconductor Chip ◽  
Thermal Cooling ◽  
The Impact

ABSTRACTHigh Performance Integrated Circuits form the basic building blocks of modern electronic systems that are designed to process ever larger numbers of electrical signals at greater signal velocity and fidelity. In such applications, each circuit must be packaged in order to provide it with necessary mechanical support, environmental protection, electrical interconnection and thermal cooling. The package, however, can also impose certain constraints on the chip. It can degrade electrical performance, add size and weight, introduce reliability problems and increase cost. Thus, packaging can be viewed as a complex balance between the provision of desired functions and the reduction of associated constraints.The ability to strike a proper balance has become increasingly difficult in recent years due to the relentless march of integrated circuits toward higher levels of complexity, size, speed, heat flux and customization. It is anticipated that the continuing evolution of high performance circuits and systems will soon be limited by the package designs and materials-of-construction, rather than by the devices on the semiconductor chip.The intent of this talk is to provide a brief overview of high performance packaging and the related materials issues. The approach is to (a) present the forecasted trends in relevant circuit performance characteristics, (b) discuss the impact of these characteristics on current chip and board level packaging methods, and (c) present new package and materials concepts that might furnish potential solutions to the developing circuit-package performance gap.

scholarly journals Electrical and Mechanical Analysis of Different TSV Geometries

Metals ◽  
2020 ◽  
Vol 10 (4) ◽  
pp. 467
Author(s):  
Il Ho Jeong ◽  
Alireza Eslami Majd ◽  
Jae Pil Jung ◽  
Nduka Nnamdi Ekere
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Signal Transmission ◽  
Characteristic Impedance ◽  
Electrical Signal ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Silicon Chips ◽  
The Impact

Through-silicon via (TSV) is an important component for implementing 3-D packages and 3-D integrated circuits as the TSV technology allows stacked silicon chips to interconnect through direct contact to help facilitate high-speed signal processing. By facilitating the stacking of silicon chips, the TSV technology also helps to meet the increasing demand for high density and high performance miniaturized electronic products. Our review of the literature shows that very few studies have reported on the impact of TSV bump geometry on the electrical and mechanical characteristics of the TSV. This paper reports on the investigation of different TSV geometries with the focus on identifying the ideal shapes for improved electrical signal transmission as well as for improved mechanical reliability. The cylindrical, quadrangular (square), elliptical, and triangular shapes were investigated in our study and our results showed that the quadrangular shape had the best electrical performance due to good characteristic impedance. Our results also showed that the quadrangular and cylindrical shapes provided improved mechanical reliability as these two shapes lead to high Cu protrusion of TSV after the annealing process.

scholarly journals Graphene Growth and Characterization: Advances, Present Challenges and Prospects

2019 ◽  
Vol 8 (4) ◽  
pp. 37
Author(s):  
John U. Arikpo ◽  
Michael U. Onuu
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Frequency Multiplier ◽  
Optical Modulator ◽  
Super Capacitor ◽  
Graphene Growth ◽  
Dielectric Substrates ◽  
Substrate Engineering ◽  
Computational Analyses ◽  
The Impact

It is about a decade since graphene became a material for serious research by researchers in condensed matter of various nationalities making significant progress. This paper on graphene growth and characterization: advances, present challenges and prospects is therefore timely. Basic topics such as graphene and graphene technology, history and trend of graphene as well as graphene growth and synthesis have been discussed. Also presented are fundamental and mechanical properties, structural and morphological property characterization using different techniques. Graphene in biomedical and radio frequency applications, transparent electronics, integrated circuits, quantum dots, frequency multiplier, optical modulator and piezoelectricity and as a battery super capacitor are some applications and uses of graphene that have been considered. The lowering of the growth temperature of graphene has been found to be beneficial for the compartibility with other materials and processes and could also decrease the impact of cooling-induced wrinkling on the morphology of graphene; the growth on dielectric substrates; being able to resolve many problems associated with metallic growth substrates; better control of both the formation and the extension of additional layers on the graphene through substrate engineering that will result in approaches of graphene that is envisaged are some of the advances and future prospects. Also, the proposed tunable bandgap for graphene which is essential for microelectronics which contributes one of the present challenges is likely to be achieved in the very near future. Although theoretical and computational analyses have proved to have solved the zero bandgap problem of graphene, more convincing approaches that will solve the problem and give way for the fabrication of high performance graphene device are being awaited.

scholarly journals Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

Technologies ◽  
2020 ◽  
Vol 8 (2) ◽  
pp. 25 ◽  
Author(s):  
Zahira Perez-Rivera ◽  
Esteban Tlelo-Cuautle ◽  
Victor Champac
Keyword(s):  
Standard Deviation ◽  
Integrated Circuits ◽  
Computing Time ◽  
Process Variations ◽  
Path Selection ◽  
Economic Losses ◽  
Gate Sizing ◽  
Circuit Performance ◽  
Average Percentage ◽  
The Impact

The impact of process variations on circuit performance has become more critical with the technological scaling, and the increasing level of integration of integrated circuits. The degradation of the performance of the circuit means economic losses. In this paper, we propose an efficient statistical gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. A path selection method, a heuristic, two coarse selection metrics, and one fine selection metric are part of the new proposed methodology. The fine metric includes essential concepts like the derivative of the standard deviation of delay, a path segment analysis, the criticality, the slack-time, and area. The proposed new methodology is applied to ISCAS Benchmark circuits. The average percentage of optimization in the delay is 12%, the average percentage of optimization in the delay standard deviation is 27.8%, the average percentage in the area increase is less than 5%, and computing time is up to ten times less than using analytical methods like Lagrange Multipliers.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

scholarly journals Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design

2017 ◽  
Vol 27 (03n04) ◽  
pp. 1750006 ◽  
Author(s):  
Farhad Merchant ◽  
Anupam Chattopadhyay ◽  
Soumyendu Raha ◽  
S. K. Nandy ◽  
Ranjani Narayan
Keyword(s):  
Linear Algebra ◽  
High Performance ◽  
Graphics Processing Unit ◽  
Building Blocks ◽  
General Purpose ◽  
Performance Tuning ◽  
Floating Point ◽  
Processing Unit ◽  
Field Programmable ◽  
The Impact

Basic Linear Algebra Subprograms (BLAS) and Linear Algebra Package (LAPACK) form basic building blocks for several High Performance Computing (HPC) applications and hence dictate performance of the HPC applications. Performance in such tuned packages is attained through tuning of several algorithmic and architectural parameters such as number of parallel operations in the Directed Acyclic Graph of the BLAS/LAPACK routines, sizes of the memories in the memory hierarchy of the underlying platform, bandwidth of the memory, and structure of the compute resources in the underlying platform. In this paper, we closely investigate the impact of the Floating Point Unit (FPU) micro-architecture for performance tuning of BLAS and LAPACK. We present theoretical analysis for pipeline depth of different floating point operations like multiplier, adder, square root, and divider followed by characterization of BLAS and LAPACK to determine several parameters required in the theoretical framework for deciding optimum pipeline depth of the floating operations. A simple design of a Processing Element (PE) is presented and shown that the PE outperforms the most recent custom realizations of BLAS and LAPACK by 1.1X to 1.5X in GFlops/W, and 1.9X to 2.1X in Gflops/mm2. Compared to multicore, General Purpose Graphics Processing Unit (GPGPU), Field Programmable Gate Array (FPGA), and ClearSpeed CSX700, performance improvement of 1.8-80x is reported in PE.

scholarly journals Low Power and High Performance MTCMOS Conditional Discharge Flip Flop

2019 ◽  
Vol 8 (6S2) ◽  
pp. 341-345
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Leakage Power ◽  
Battery Life ◽  
Flip Flop ◽  
Circuit Performance ◽  
Processing Information ◽  
Conditional Discharge ◽  
Standby Mode

Utilization in high-performance integrated circuits has been one of the most severe limitations in models in recent years.. Conditional discharge flip flop (CDFF) related to one of the earliest pulses caused flipflop reduces internal switching activities as that of existing explicit pulse triggered Data close to output flipflop (Ep-DCO). Registers are the main parts for processing information eg: in counters, accumulators etc.,. Implementation of these registers using CDFF can achieve low power consumption and high performance. MTCMOS (multi threshold CMOS) technique saves the leakage power during standby mode operations and hence, enhances the circuit performance for long battery life applications. We find that, using both MTCMOS and conditional discharge technique in flip flop, improves the performance and also consumes low power. In this paper, we simulate CDFF and the proposed MTCMOS CDFF to prove that MTCMOS CDFF is the best among the fastest pulse triggered flipflops. We also implement an application 4 bit shift register using proposed MTCMOS conditional discharge flip flop

Metallization for Integrated Circuit Manufacturing

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 33-37 ◽  
Author(s):  
R.V. Joshi ◽  
R.S. Blewer ◽  
S. Murarka
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Performance ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Random Access ◽  
Circuit Performance ◽  
Integrated Circuit Manufacturing ◽  
The 1960S ◽  
Al Metallization

This issue of the MRS Bulletin focuses on current interconnect metallurgies practiced in the manufacturing of integrated circuits (ICs). The issue should serve as a reference for researchers, scientists, engineers, and those who are not familiar with the IC arena.Al-metallization requires special attention due to its wide usage in logic and memory circuits. Logic requirements drive technology toward improved circuit performance while memory improvements require high device and wiring densities. As the dynamic random access memory (DRAM) evolves from 64 Mbits to 256 Mbits, ultralarge-scale integrated (ULSI) wiring will decrease to below sub-0.3 μm in dimensions. Such circuits require robust, reliable back end of the line (BEOL) technology that meets high-performance, low-cost, stringent electromigration requirements. We feel that several of these emerging interconnect fabrication techniques have reached a sufficient level of maturity to warrant a reasonable exposition. We will concentrate on metallization systems in this issue, leaving a discussion of dielectrics for the future, due to space limitations.The semiconductor industry has relied on aluminum technology since the 1960s because it is a well-established, low-cost technology. Early improvements in the electromigration resistance of Al lines by the addition of Cu impurities after 1971 helped this metallurgy to endure further feature size reductions, without degradation of reliability. However, the relentless reduction in via and line size once again may bring into question the limitation of Al reliability. As a result, work on alternate low-resistivity and high-electromigration-resistant metals like Cu is continuing in parallel.

GEOSX: A Multiphysics, Multilevel Simulator Designed for Exascale Computing

2021 ◽  
Author(s):  
Herve Gross ◽  
Antoine Mazuyer
Keyword(s):  
Reservoir Simulation ◽  
High Performance ◽  
Lawrence Livermore National Laboratory ◽  
National Laboratory ◽  
Building Blocks ◽  
Open Architecture ◽  
Simulation Tool ◽  
Simulation Tools ◽  
Basin Scale ◽  
The Impact

Abstract Evaluating large basin-scale formations for CO2 sequestration is one of the most important challenges for our industry. The technical complexity and the quantification of risks associated with these operations call for new reservoir engineering and reservoir simulation tools. The impact of multiple coupled physical phenomena, the century timescale, and basin-sized models in these operations force us to completely take apart and revisit the numerical backbone of existing simulation tools. We need a reservoir simulation tool designed for scalability and portability on high-performance computing architectures. To achieve this, we are proposing a new, open-source, multiphysics, and multilevel physics simulation tool called GEOSX. This tool is jointly created by Lawrence Livermore National Laboratory, Stanford University, and Total. It is designed for scalability on multiple CPUs and multiple GPUs and offers a suite of physical solvers that can be extended easily while achieving a balance between performance and portability. GEOSX is initially targeting multiphysics simulations with coupled geomechanics, flow, and transport mechanics but with its open architecture, it allows access to high-performance physical solvers as building blocks of other multiphysics problems and provides users with a suite of tools for numerical optimization across platforms. In this paper, we introduce GEOSX, expose its fundamental architecture principles, and show an example of geological sequestration of CO2 modeling on real data. We demonstrate our ability to simulate fluid and rock poromechanical interactions over long periods and basin-scale dimensions. GEOSX demonstrates its usefulness for such complex and large problems and proves to be scalable and portable across multiple high-performance systems.

scholarly journals Influence of Flexibility of the Interconnects on the Dynamic Bending Reliability of Flexible Hybrid Electronics

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 238 ◽  
Author(s):  
Nagarajan Palavesam ◽  
Waltraud Hell ◽  
Andreas Drost ◽  
Christof Landesberger ◽  
Christoph Kutter ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Electronic Systems ◽  
Test Results ◽  
Limited Information ◽  
Silicon Integrated Circuits ◽  
Series Of Experiments ◽  
Dynamic Bending ◽  
Flexible Metal ◽  
Flexible Foils

The growing interest towards thinner and conformable electronic systems has attracted significant attention towards flexible hybrid electronics (FHE). Thin chip-foil packages fabricated by integrating ultra-thin monocrystalline silicon integrated circuits (ICs) on/in flexible foils have the potential to deliver high performance electrical functionalities at very low power requirements while being mechanically flexible. However, only very limited information is available regarding the fatigue or dynamic bending reliability of such chip-foil packages. This paper reports a series of experiments where the influence of the type of metal constituting the interconnects on the foil substrates on their dynamic bending reliability has been analyzed. The test results show that chip-foil packages with interconnects fabricated from a highly flexible metal like gold endure the repeated bending tests better than chip-foil packages with stiffer interconnects fabricated from copper or aluminum. We conclude that further analysis work in this field will lead to new technical concepts and designs for reliable foil based electronics.

scholarly journals Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

Micromachines ◽  
2018 ◽  
Vol 10 (1) ◽  
pp. 6 ◽  
Author(s):  
Jürgen Lorenz ◽  
Eberhard Bär ◽  
Sylvain Barraud ◽  
Andrew Brown ◽  
Peter Evanschitzky ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Process Variations ◽  
Electrical Performance ◽  
Process Equipment ◽  
Process Variability ◽  
Circuit Performance ◽  
Technological Challenge ◽  
Device Properties ◽  
The Impact ◽  
Full Simulation

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.

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