scholarly journals Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

Technologies ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 38
Author(s):  
Santthosh Selvaraj ◽  
Erkan Bayram ◽  
Renato Nega
Keyword(s):  
High Stability ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
System Level ◽  
Digital Controller ◽  
Noise Performance ◽  
Different Types ◽  
Digitally Controlled ◽  
Phase Noise Performance ◽  
Simulation Results

This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.4% and 8.5% for the DAC-based and controller-based DCO, respectively. The phase noise performance of the DAC-based DCO and controller-based DCO is −78.9 dBc/Hz and −81.3 dBc/Hz at 1 MHz offset, respectively. The implementations are given and compared according to their performance based on post-layout simulation results.

Ring Oscillator Phase Noise Properties due to PSN with Deterministic Frequency

2012 ◽  
Vol 496 ◽  
pp. 527-533
Author(s):  
Na Bai ◽  
Hong Gang Zhou ◽  
Qiu Lei Wu ◽  
Chun Yu Peng
Keyword(s):  
Phase Noise ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Analysis Method ◽  
Noise Performance ◽  
Supply Noise ◽  
Total Phase ◽  
Phase Noise Performance ◽  
Oscillator Phase Noise ◽  
Oscillator Phase

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

AN EFFICIENT LOW-POWER SIGMA-DELTA MODULATOR FOR MULTI-STANDARD WIRELESS APPLICATIONS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Cmos Technology ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Design And Implementation ◽  
Simulation Results ◽  
System Level Simulations

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.

15 GHz quadrature voltage controlled oscillator in 130 nm CMOS technology

2011 ◽  
Vol 3 (6) ◽  
pp. 627-631 ◽  
Author(s):  
Paolo Lucchi ◽  
Davide Dermit ◽  
Gilles Jacquemod ◽  
Jean Baptiste Begueret ◽  
Mattia Borgarino
Keyword(s):  
Phase Noise ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Noise Performance ◽  
Commercial Products ◽  
Satellite Applications ◽  
Phase Noise Performance

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

Noise performance comparison between two different types of time-domain systems for microwave detection

2016 ◽  
Vol 9 (3) ◽  
pp. 535-542 ◽  
Author(s):  
Xuezhi Zeng ◽  
Albert Monteith ◽  
Andreas Fhager ◽  
Mikael Persson ◽  
Herbert Zirath
Keyword(s):  
Time Domain ◽  
Random Sequence ◽  
Random Noise ◽  
Performance Comparison ◽  
System Level ◽  
Noise Performance ◽  
Microwave Detection ◽  
Study Results ◽  
Different Types ◽  
Noise Sequence

This paper compares the noise performance of two different types of time-domain microwave detection systems: a pulsed system and a pseudo-random noise sequence system. System-level simulations and laboratory-based measurements are carried out in the study. Results show that the effect of timing jitter is more significant on the measurement accuracy of the pseudo-random noise sequence system than that of the pulsed system. Although the signal power density of the pseudo-random sequence system is tens of dBs higher than that of the pulsed system over the frequency band of interest, the signal-to-noise ratio difference between these two systems can be just a few dBs or even smaller depending on the jitter level.

scholarly journals Ka Band Phase Locked Loop Oscillator Dielectric Resonator Oscillator for Satellite EHF Band Receiver

2008 ◽  
Vol 2008 ◽  
pp. 1-6
Author(s):  
S. Coco ◽  
F. Di Maggio ◽  
A. Laudani ◽  
I. Pomona
Keyword(s):  
Dielectric Resonator ◽  
Local Oscillator ◽  
Low Noise ◽  
Noise Performance ◽  
Ka Band ◽  
Phase Noise Performance ◽  
Fundamental Oscillation ◽  
Simulation Results ◽  
Very High ◽  
Good Agreement

This paper describes the design and fabrication of a Ka Band PLL DRO having a fundamental oscillation frequency of 19.250 GHz, used as local oscillator in the low-noise block of a down converter (LNB) for an EHF band receiver. Apposite circuital models have been created to describe the behaviour of the dielectric resonator and of the active component used in the oscillator core. The DRO characterization and measurements have shown very good agreement with simulation results. A good phase noise performance is obtained by using a very highQdielectric resonator.

A new tail-switching superharmonic multiphase LC-VCO

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Emad Ebrahimi
Keyword(s):  
Phase Noise ◽  
Communication Systems ◽  
Figure Of Merit ◽  
Noise Performance ◽  
Pass Filter ◽  
Content Type ◽  
Voltage Controlled Oscillators ◽  
Coupling Capacitor ◽  
Phase Noise Performance ◽  
Simulation Results

Purpose Multiphase and quadrature voltage-controlled oscillators (QVCOs) play key roles in modern communication systems and their phase noise performance affects the performance of the overall system. Different studies are devoted to efficient quadrature signals generation. This paper aims to present a new low-phase noise superharmonic injection-locked QVCO. Design/methodology/approach The proposed QVCO is comprised of two identical inductor-capacitor circuit (LC)-voltage-controlled oscillators (VCOs) in which second harmonics, with 180° phase shift, are injected from one core VCO to the gate of tail current source of the other VCO via a coupling capacitor. Using second harmonics with high amplitude will switch the tail from the inversion to the accumulation, and therefore, flicker noise is reduced. Also, because of the use of lossless and noiseless coupling elements, that is, coupling capacitors, and also because of the existence of an inherent high-pass filter, the proposed LC-QVCO has a good phase noise performance. Findings The introduced technique is designed and simulated in a commercial 0.18 µm radio frequency complementary metal oxide semiconductor (RF-CMOS) technology and 10 dB improvement of close-in phase noise is achieved (compared to the conventional method). Simulation results show that the phase noise of the proposed QVCO is −130.3 dBc/Hz at 3 MHz offset from 5.76 GHz center frequency, while the total direct current (DC) current drawn from a 0.9-V power supply is 4.25 mA (figure of merit = −190.2 dBc). Monte Carlo simulation results show that the figure of merit of the circuit has a Gaussian distribution with mean value and standard deviation of −189.97 dBc and 0.183, respectively. Originality/value This technique provides a new simple but efficient superharmonic coupling and noise shaping method that reduces close-in phase noise of superharmonic multiphase VCOs by switching of tail transistors with 2 ω0 (second harmonic of oscillation frequency). No extra devices such as area-consuming transformer or additional power-hungry oscillator are used for coupling.

A Current Reused Divided-by-Two Frequency Divider

2013 ◽  
Vol 660 ◽  
pp. 119-123
Author(s):  
Xiao Shi ◽  
Fu Qing Huang ◽  
Zhi Lin Liu ◽  
Jian Hui Wu
Keyword(s):  
Process Simulation ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Frequency Divider ◽  
Cmos Process ◽  
Noise Performance ◽  
Low Power Dissipation ◽  
Phase Noise Performance ◽  
Simulation Results ◽  
A Current

In this paper, a low power dissipation divide-by-two frequency divider is presented. The master latch and the slave latch of the divide-by-two frequency divider are stacked in cascode to reuse the current. The frequency divider can operate with only half the current of a conventional divider. A divide-by-two frequency divider based on the proposed topology is designed and simulated in a 0.18μm 1P6M CMOS process. Simulation results show the frequency divider can operate up to 11GHz with only 0.66mW power dissipation under 1.8V supply voltage. And it also demonstrates good phase noise performance.

scholarly journals RF CMOS Oscillators Design for autonomous Connected Objects

2019 ◽  
Vol 88 ◽  
pp. 05001
Author(s):  
Fayrouz Haddad ◽  
Wenceslas Rahajandraibe ◽  
Imen Ghorbel
Keyword(s):  
Performance Optimization ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Noise Performance ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Cmos Oscillators ◽  
Phase Noise Performance

Voltage controlled oscillator (VCO) is an integral part of IoT wireless transceiver components. In this paper, VCOs operating around 2.4 GHz have been designed in CMOS technology. The relation between their components and specifications is studied for their performance optimization. Ultra-low power, less than 270 µW, has been obtained, while performing a frequency tuning range of about 10% between 2.1 and 2.4 GHz. Investigations on phase noise performance have been also achieved.

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