scholarly journals Design Of Low Power 6t-Sram Cell For Advanced Processors

2019 ◽  
Vol 8 (6S) ◽  
pp. 946-954
Keyword(s):  
Supply Voltage ◽  
Random Access ◽  
Data Retention ◽  
Static Noise Margin ◽  
Information Retention ◽  
Noise Margin ◽  
Sram Cell ◽  
Control Application ◽  
With Memory ◽  
Static Noise

The Static Random Access Memory (SRAM) is one of the feature of the robotized world. Everything thought of it as, channels creature level of intensity & bomb wretchedly zone. In that point of confinement wide investigate in the SRAM is an advancing related power dispersal, memory chip zone & supply voltage major. This paper SRAM assessment to the degree Static Noise Margin, Data Retention Voltage, Read Margin & Write Margin for low control application is considered. The Static Noise Margin (SNM) is one of the very peak head for essentials of dealing with memory since it effects read edge sensibly as the structure_ edge. In the SRAM cell SNM is identified with the NMOS & PMOS contraption's most purged point respects. The High Read & Write Noise Margin is other than true bugs in the structure of the SRAM information retention Voltage is consented to 6T-SRAM cell for the applications requiring lively works out. The Various sorts of wind are taken unmistakably to examinations to the 6t-SRAM by fluctuating the size of the transistor. The Execution appraisal is examined in 6T-SRAM oversaw and finished in 32nm progression.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability

2019 ◽  
Vol 29 (05) ◽  
pp. 2050067
Author(s):  
S. R. Mansore ◽  
R. S. Gamad ◽  
D. K. Mishra
Keyword(s):  
High Performance ◽  
Model Simulation ◽  
Random Access ◽  
Leakage Power ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Operation Characteristics ◽  
Static Noise

Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

scholarly journals VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY

2011 ◽  
Vol 12 (1) ◽  
pp. 13-30 ◽  
Author(s):  
Aminul Islam ◽  
Mohd. Hasan
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Static Random Access Memory ◽  
Access Time ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Pvt Variations ◽  
Static Noise

This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM).

scholarly journals A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array

2018 ◽  
Vol 7 (2.20) ◽  
pp. 109
Author(s):  
S Renukarani ◽  
Bhavana Godavarthi ◽  
SK Bia Roshini ◽  
Mohammad Khadir
Keyword(s):  
Dynamic Control ◽  
Random Access ◽  
Memory Cell ◽  
Dynamic Feedback ◽  
Cell Array ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Ram ◽  
Static Noise

A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to sub-nanometer engineering technology.  

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

2021 ◽  
Author(s):  
Yihan Zhu ◽  
Takashi Ohsawa
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Gate Insulator ◽  
Gate Leakage ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Sram Cell ◽  
Conventional Cell ◽  
P Type ◽  
Static Noise

Abstract A novel loadless four-transistor static random access memory cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32nm technology node that the read static noise margin of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold static noise margin can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

scholarly journals Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

2021 ◽  
Vol 10 (2) ◽  
pp. 130
Author(s):  
Ram Murti Rawat ◽  
Vinod Kumar
Keyword(s):  
Random Access ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Engineering Level ◽  
Sram Cell ◽  
Improved Stability ◽  
Cell Segment ◽  
Static Noise

<span>This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.</span>

scholarly journals Restoration circuits for Low power Reduce Swing of 6T and 8T SRAM Cell With Improved Read and Write Margins

2021 ◽  
Vol 7 ◽  
pp. 22-34
Author(s):  
Vinod Kumar ◽  
Ram Murti Rawat
Keyword(s):  
Low Power ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Equivalent Time ◽  
Sram Cell ◽  
Section Viii ◽  
Static Noise

A paper that examines the factors thataffect the Static Noise Margin (SNM) of a StaticRandom Access memories. At an equivalent time,they specialise in optimizing Read and Writeoperation of 8T SRAM cell which is best than 6TSRAM cell Using Swing Restoration Dual NodeVoltage. The read and Write operation and improveStability analysis. This SRAM technique on thecircuit or architecture level is required to improveread and write operation. during this paperComparative Analysis of 6T and 8T SRAM Cellswith Improved Read and Write Margin is completedfor 180 nm Technology with Cadence Virtuososchematics Tool.This Paper is organized as follows: thecharacteristics of 6T SRAM cell are described arerepresented in section VIII. In section IX, proposed8T SRAM cell is described. In section X, Standard8T SRAM cell is described. Section XI includes thesimulation results which give comparison of variousparameters of 6T and 8T SRAM cells. In Section XIISimulation Results and DC analysis and sectionXIII conclusion the work.

Sign in / Sign up

Export Citation Format

Share Document