scholarly journals Reduction of Test Time using Multiple Test Control Point Insertion for 7nm Technology Node

2020 ◽  
Vol 9 (5) ◽  
pp. 1957-1960
Keyword(s):  
Control Point ◽  
Vlsi Design ◽  
Software Tool ◽  
Cost Effective ◽  
Standard Test ◽  
Test Reliability ◽  
Design Rule ◽  
Test Time ◽  
Technology Node ◽  
Test Control

Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test. Reliability and testability both are main objectives for DFT in today’s VLSI design. In this paper, we have proposed multiple standard test control point insertion technique for 7nm technology node. The design was tested on 7828 sequential cells. We have compared results of following three Design Rule Check (DRC) (1) Scan DRC (2) Clock Scan DRC (3) Multiple standard test control point insertion DRC. We have used software tool Synopsys TetraMAX ATPG, Synopsys DFTMAX and Synopsys DFT compiler to verify the design. It has been observed that multiple standard test control point insertion DRC takes minimum time to check design of 7828 sequential cells.

scholarly journals Food Allergen Detection Methods: A Coordinated Approach

2004 ◽  
Vol 87 (6) ◽  
pp. 1383-1390 ◽  
Author(s):  
Philip R Goodwin
Keyword(s):  
Hazard Analysis ◽  
Adult Population ◽  
Control Point ◽  
Cost Effective ◽  
Test Methods ◽  
Detection Methods ◽  
Critical Control Point ◽  
Life Threatening ◽  
Monitoring And Surveillance ◽  
Analytical Approaches

Abstract The levels (1–2%) and increasing severity of allergic responses to food in the adult population are well documented, as is the phenomenon of even higher (3–8%) and apparently increasing incidence in children, albeit that susceptibility decreases with age. Problematic foods include peanut, milk, eggs, tree nuts, and sesame, but the list is growing as awareness continues to rise. The amounts of such foods that can cause allergic reactions is difficult to gauge; however, the general consensus is that ingestion of low parts per million is sufficient to cause severe reactions in badly affected individuals. Symptoms can rapidly—within minutes—progress from minor discomfort to severe, even life-threatening anaphylactic shock in those worst affected. Given the combination of high incidence of atopy, potential severity of response, and apparently widespread instances of “hidden” allergens in the food supply, it is not surprising that this issue is increasingly subject to legislative and regulatory scrutiny. In order to assist in the control of allergen levels in foods to acceptable levels, analysts require a combination of test methods, each designed to produce accurate, timely, and cost-effective analytical information. Such information contributes significantly to Hazard Analysis Critical Control Point programs to determine food manufacturers’ risk and improves the accuracy of monitoring and surveillance by food industry, commercial, and enforcement laboratories. Analysis thereby facilitates improvements in compliance with labeling laws with concomitant reductions in risks to atopic consumers. This article describes a combination of analytical approaches to fulfill the various needs of these 3 analytical communities.

scholarly journals Deep sequencing of DNA from urine of kidney allograft recipients to estimate donor/recipient-specific DNA fractions

PLoS ONE ◽  
2021 ◽  
Vol 16 (4) ◽  
pp. e0249930
Author(s):  
Aziz Belkadi ◽  
Gaurav Thareja ◽  
Darshana Dadhania ◽  
John R. Lee ◽  
Thangamani Muthukumar ◽  
...  
Keyword(s):  
Dna Sequencing ◽  
Bacterial Infections ◽  
Human Kidney ◽  
Cost Effective ◽  
Maximum Error ◽  
Standard Test ◽  
Kidney Allograft ◽  
Cost Effective Method ◽  
In Silico Simulation ◽  
End Stage

Kidney transplantation is the treatment of choice for patients with end-stage kidney failure, but transplanted allograft could be affected by viral and bacterial infections and by immune rejection. The standard test for the diagnosis of acute pathologies in kidney transplants is kidney biopsy. However, noninvasive tests would be desirable. Various methods using different techniques have been developed by the transplantation community. But these methods require improvements. We present here a cost-effective method for kidney rejection diagnosis that estimates donor/recipient-specific DNA fraction in recipient urine by sequencing urinary cell DNA. We hypothesized that in the no-pathology stage, the largest tissue types present in recipient urine are donor kidney cells, and in case of rejection, a larger number of recipient immune cells would be observed. Extensive in-silico simulation was used to tune the sequencing parameters: number of variants and depth of coverage. Sequencing of DNA mixture from 2 healthy individuals showed the method is highly predictive (maximum error < 0.04). We then demonstrated the insignificant impact of familial relationship and ethnicity using an in-house and public database. Lastly, we performed deep DNA sequencing of urinary cell pellets from 32 biopsy-matched samples representing two pathology groups: acute rejection (AR, 11 samples) and acute tubular injury (ATI, 12 samples) and 9 samples with no pathology. We found a significant association between the donor/recipient-specific DNA fraction in the two pathology groups compared to no pathology (P = 0.0064 for AR and P = 0.026 for ATI). We conclude that deep DNA sequencing of urinary cells from kidney allograft recipients offers a noninvasive means of diagnosing acute pathologies in the human kidney allograft.

Test Reliability of Impurity Parameters of Uster AFIS

2011 ◽  
Vol 331 ◽  
pp. 516-527
Author(s):  
Peng Zi Sun ◽  
Ji Peng Cao
Keyword(s):  
Statistical Analysis ◽  
Test Reliability ◽  
Test Time ◽  
Test Results ◽  
Analysis Method ◽  
Sample Weight ◽  
Reliable Test ◽  
Sampling Process ◽  
Statistical Analysis Method ◽  
Card Sliver

This paper presents test reliablity of Uster AFIS for impurity test by calculating the Reliable Test Time (hereinafter referred to as RTT) and CV% of test results. The CV% value of test results of impurity-related parameters in card sliver obtained in 8 experiments totally with 313 different plans were calculated. By statistical analysis method, the reliable test time of AFIS for some impurity-related parameters was estimated. It is concluded that the impurity result obtained by 10-time tests with AFIS was inaccurate. The reasons for this are that the sample weight is too small, the impurity is unevenly distributed and the impurity in card sliver may have some loss in the manually-sampling process.

Multi-Fuel Power Dispatch Considering Prohibited Operating Zones and Tie-Line Flow Limits Using Ant Lion Optimizer

2021 ◽  
pp. 223-255
Author(s):  
Ganesan Sivarajan ◽  
Jayakumar N. ◽  
Balachandar P. ◽  
Subramanian Srikrishna
Keyword(s):  
Electrical Power ◽  
Cost Effective ◽  
Standard Test ◽  
Fuzzy Decision Making ◽  
Prohibited Operating Zones ◽  
Ant Lion Optimizer ◽  
Line Flow ◽  
Plant Operations ◽  
Ant Lion ◽  
Tie Line

The electrical power generation from fossil fuel releases several contaminants into the air, and these become excrescent if the generating unit is fed by multiple fuel sources (MFS). The ever more stringent environmental regulations have forced the utilities to produce electricity at the cheapest price and the minimum level of pollutant emissions. The restriction in generator operations increases the complexity in plant operations. The cost effective and environmental responsive operations in MFS environment can be recognized as a multi-objective constrained optimization problem. The ant lion optimizer (ALO) has been chosen as an optimization tool for solving the MFS dispatch problems. The fuzzy decision-making mechanism is integrated in the search process of ALO to fetch the best compromise solution (BCS). The intended algorithm is implemented on the standard test systems considering the prevailing operational constraints such as valve-point loadings, CO2 emission, prohibited operating zones and tie-line flow limits.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

2014 ◽  
Vol 2014 (1) ◽  
pp. 000599-000605 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Cost Effective ◽  
Disruptive Innovation ◽  
Design Rule ◽  
Wind Condition ◽  
Silicon Etching ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

2015 ◽  
Vol 12 (3) ◽  
pp. 111-117
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Integration ◽  
Cost Effective ◽  
Design Rule ◽  
Innovative Technology ◽  
Wind Condition ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

scholarly journals Overview of Affinity Biosensors in Food Analysis

2006 ◽  
Vol 89 (3) ◽  
pp. 805-818 ◽  
Author(s):  
Pradip D Patel
Keyword(s):  
Driving Forces ◽  
Hazard Analysis ◽  
Control Point ◽  
Cost Effective ◽  
Industrial Test ◽  
Market Growth ◽  
Critical Control Point ◽  
Industrial Sectors ◽  
Legislative Framework ◽  
Affinity Biosensors

Abstract The 4 major driving forces that are expected to lead to increased use of affinity biosensors that meet crucial industrial test specifications, e.g., fast, reliable, cost-effective, and use of low-skilled personnel, are (1) strict legislative framework, e.g., recent changes proposed to the European food safety and hygiene legislation, EC No. 178/2002; (2) industrial shift from quality control to quality assurance procedures, e.g., Hazard Analysis Critical Control Point, ensuring effective positioning in the global competitive trade; (3) just-in-time production resulting in right product every time; and (4) consumer demand for safe and wholesome products. The affinity biosensors field has expanded significantly over the past decade, with a projected global biosensors market growth from $6.1 billion in 2004 to $8.2 billion in 2009, representing major industrial sectors (e.g., Pharma, Medicare, and Food). This brief review is targeted to affinity biosensors developed for the food industry and includes research and development leading to biosensors for microbiological and chemical analytes of industrial concern, commercial biosensors products on the market, and examples of future prospects in this diagnostic field.

A Digital-Based Low-Power Fully Differential Comparator

2016 ◽  
Vol 26 (01) ◽  
pp. 1750002 ◽  
Author(s):  
Anil Singh ◽  
Ayushi Goel ◽  
Alpana Agarwal
Keyword(s):  
Low Power ◽  
Analog Circuit ◽  
Substantial Reduction ◽  
Vlsi Design ◽  
Cost Effective ◽  
Cmos Technology ◽  
Portable Devices ◽  
Design Environment ◽  
Voltage Comparator ◽  
Fully Differential

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence[Formula: see text] Virtuoso Analog Design Environment using UMC 180[Formula: see text]nm CMOS technology at 1.8[Formula: see text]V supply.

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