High-Speed Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques

2010 ◽  
Vol 459 ◽  
pp. 260-270
Author(s):  
Yasushi Yuminaka ◽  
Kenichi Henmi
Keyword(s):  
Time Domain ◽  
Data Transmission ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Pulse Amplitude ◽  
Cmos Technology ◽  
Timing Resolution ◽  
Channel Effects ◽  
Domain Information ◽  
Lower Voltage

This paper describes a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower voltage headroom. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects.

scholarly journals A Time-Overlapping Multiplex VLC System for End-Edge Data Transmission

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Tingting Fu ◽  
Huanghong Zhu ◽  
Han Hai ◽  
Haksrun Lao
Keyword(s):  
Data Transmission ◽  
Electromagnetic Interference ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Transmission Rate ◽  
Pulse Amplitude ◽  
Visible Light Communication ◽  
Radio Communications ◽  
Environmental Light ◽  
New Type

Communication is one of the most important foundations in the Internet of Things. Although some cutting-edge technologies, such as 5G, have greatly empowered edge computing, electromagnetic interference and pollution make them impracticable in many environments. The visible light communication (VLC) is a new type of wireless communication technology with appealing benefits not presented in radio communications. VLC allows a lamp or other light source to not only serve as illumination but also simultaneously transmit data. Although traditional VLC multiplexing technologies have been able to achieve a high-speed data transmission rate, they require all receivers to use the same modulation means. In many scenarios, various-type receivers coexist; it is costly to incorporate multiple senders to implement adaptive content distribution in on-demand services. In this paper, we propose a new type of VLC multiplexing system, which realizes end-edge data transmission through pulse position modulation (PPM), pulse width modulation (PWM), and pulse amplitude modulation (PAM) simultaneously. Therefore, one edge server can serve multiple types of end-users without interference. In order to evaluate the performance of the system, we conduct experiments with different settings of communication distance, communication angle, and different environmental light conditions. For three modulations, the proposed system can achieve a transmission speed three times as that for a single modulation, and reach the accuracy rate of up to 99% within the proper communication range.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

A 2nd-Order PWM Pre-Emphasis Technique and its Experimental FPGA Implementation

2013 ◽  
Vol 534 ◽  
pp. 227-232
Author(s):  
Yasushi Yuminaka ◽  
Shingo Ishida ◽  
Kenichi Henmi
Keyword(s):  
Transfer Function ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Pulse Amplitude ◽  
Higher Order ◽  
Fpga Implementation ◽  
Proof Of Concept ◽  
Timing Resolution

In this paper, a Pulse-Width Modulation (PWM) pre-emphasis technique is extended to a2nd-order version to equalize a higher-order transfer function of an interconnection inside/betweenVLSI chips. The PWM pre-emphasis method does not change the pulse amplitude as for conventionalFIR pre-emphasis, but instead exploits timing resolution. As a proof of concept, a 2nd-order timedomainpre-emphasis technique is designed and implemented using an FPGA to demonstrate thecapability of compensating for deterioration of signals caused by interconnections with higher-ordertransfer functions.

High-Speed Data Transmissions Using Tomlinson-Harashima Precoding

2013 ◽  
Vol 596 ◽  
pp. 199-203 ◽  
Author(s):  
Yosuke Iijima ◽  
Yasushi Yuminaka
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
High Performance ◽  
Average Power ◽  
Pulse Amplitude ◽  
Coaxial Cable ◽  
Experimental Implementation ◽  
Low Pass ◽  
High Speed Data ◽  
Speed Data Transmission

High-speed interfaces become an important role to achieve high performance VLSIsystems. This paper demonstrates a high-speed data transmission technique using Tomlinson-Harashima Precoding (THP). The THP can compensate for low-pass effect of an interconnec-tion at a transmitter, and it can also limit peak and average power of a transmitted signal. Inthis paper, a 200Mbps 4-PAM(Pulse-amplitude modulation) transmitter is designed and simu-lated to demonstrate the THP performance. The experimental implementation using an FPGAdemonstrates high-speed transmission over a long 3D2V coaxial cable.

scholarly journals Improved Precoder Architecture for Duobinary Transceivers

2017 ◽  
Vol 5 ◽  
Author(s):  
Javier Aguirre Olcoz ◽  
C. Sánchez-Azqueta ◽  
E. Guerrero ◽  
C. Gimeno ◽  
S. Celma
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Cmos Technology ◽  
Modulation Scheme ◽  
Serial Data ◽  
Soi Cmos

Duobinary modulation is an attractive baseband modulation scheme for high-speed serial data transmission. This work presents a duobinary transceiver with a new precoder architecture that overcomes the glitch vulnerability of the conventional ones. It has been fabricated in a 0.13-μm PD-SOI CMOS technology and achieves 10 Gbps consuming 37 mW. 

scholarly journals A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

2019 ◽  
Vol 8 (11S) ◽  
pp. 11-19
Keyword(s):  
Comparative Analysis ◽  
High Resolution ◽  
Low Power ◽  
Time Domain ◽  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

A 0.5–1.2 V PWM CMOS DPS WITH 120 dB DYNAMIC RANGE FOR BIONIC HUMAN EYE IN DEEP SUBMICRON CMOS TECHNOLOGY

2014 ◽  
Vol 23 (02) ◽  
pp. 1450020 ◽  
Author(s):  
JIANGTAO XU ◽  
WEISONG JIN ◽  
KAIMING NIE ◽  
SUYING YAO
Keyword(s):  
High Speed ◽  
Pulse Width Modulation ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Digital Camera ◽  
Cmos Technology ◽  
Frame Rate ◽  
Clock Frequency ◽  
Human Eye ◽  
Digital Pixel

In this paper, a CMOS digital pixel sensor (DPS) with pixel-level ADC based on pulse width modulation (PWM) scheme is proposed to overcome the restriction of low supply voltage imposed by device scaling trend. The pixel operates with a dynamic current comparison scheme to avoid using complex in-pixel comparator and achieve a high dynamic range (DR). By adjusting clock frequency for different illumination, DR is further extended due to increasing the maximum detectable photocurrent and lowering the minimum detectable photocurrent. The pixel contains a photodiode (PD), an 11-bit in-pixel SRAM and other 11 transistors, and occupies an area of 7 μm × 7 μm, with a fill factor of 31.3% using a standard 65 nm CMOS technology. Simulation results show that this pixel can work at a supply voltage as low as 0.5 V with 120 dB DR and 80 dB linear DR (LDR). The properties of high DR and logarithmic response make the proposed digital pixel be capable of human eye. Frame rate achieves 246 fps with 640 × 480 pixel array by using in-pixel ADC and SRAM. This makes the digital pixel very suitable for high-speed snap shot digital camera application.

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