High Quality Uniform SiC Epitaxy for Power Device Applications

2007 ◽  
Vol 556-557 ◽  
pp. 101-104
Author(s):  
Jie Zhang ◽  
Esteban Romano ◽  
Janice Mazzola ◽  
Swapna G. Sunkari ◽  
Carl Hoff ◽  
...  

In this paper we present highly uniform SiC epitaxy in a horizontal hot-wall CVD reactor with wafer rotation. Epilayers with excellent thickness uniformity of better than 1% and doping uniformity better than 5% are obtained on 3-in, 4° off-axis substrates. The same growth conditions for uniform epitaxy also generate smooth surface morphology for the 4° epiwafers. Well controlled doping for both n- and p-type epilayers is obtained. Abrupt interface transition between n- and pdoped layers in a wide doping range is demonstrated. Tight process control for both thickness and doping is evidenced by the data collected from the epi operations. The average deviation from target is 2.5% for thickness and 6% for doping. PiN diodes fabricated on a standard 3-in, 4° epiwafer have shown impressive performance. More than half of the 1 mm2 devices block 1 kV (2.3 MV/cm) with a low leakage current of 1 μA.

2000 ◽  
Vol 622 ◽  
Author(s):  
Margarita P. Thompson ◽  
Gregory W. Auner ◽  
Changhe Huang ◽  
James N. Hilfiker

ABSTRACTAlN films with thicknesses from 53 to 79 nm were deposited on 6H-SiC substrates via Plasma Source Molecular Beam Epitaxy (PSMBE). The influence of deposition temperature on the growth mode and film roughness was assessed. The optical constants of the films in the range 0.73-8.75 eV were determined using spectroscopic ellipsometry. Pt/AlN/6H-SiC MIS structures were created and current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed at room temperature and at 250°C. Most of the MIS structures showed rectifying I-V characteristics regardless of growth temperature. A 120-nm-thick AlN film was deposited at 500°C. MIS structures created on this film showed a very low leakage current densities of 6×10−8 A/cm2. The dielectric constant of the film was estimated at approximately 9. The relation between film structure and electrical properties of the films is discussed.


1982 ◽  
Vol 16 ◽  
Author(s):  
A. Musa ◽  
J.P. Ponpon ◽  
M. Hage-Ali

ABSTRACTOhmic and rectifying contacts on high resistivity etched P-type cadmium telluride have been studied in order to produce diode structures.For this,we have first investigated the properties of gold contacts obtained by chemical reactions of CdTe dippedin gold chloride.Both electrical characterization and structure have been analyzed as a function of the experimental conditions of the contact deposition.The results can be interpreted in terms of a current flow enhanced by tunnelling through the Au-CdTe junction and related to the structure of the interface a few tens of nanometer below the gold contact. In addition,several rectifying contacts have been investigated , in order to achieve a structure having low leakage current.


2017 ◽  
Vol 897 ◽  
pp. 63-66
Author(s):  
Selsabil Sejil ◽  
Loic Lalouat ◽  
Mihai Lazar ◽  
Davy Carole ◽  
Christian Brylinski ◽  
...  

This study deals with the electrical characterization of PiN diodes fabricated on a 4°off-axis 4H-SiC n+ substrate with a n- epilayer (1×1016 cm-3 / 10 µm). Optimized p++ epitaxial areas were grown by Vapour-Liquid-Solid (VLS) transport to form p+ emitters localized in etched wells with 1 µm depth. Incorporated Al level in the VLS p++ zones was checked by SIMS (Secondary Ion Mass Spectroscopy), and the doping level was found in the range of 1-3×1020 at.cm-3. Electrical characterizations were performed on these PiN diodes, with 800 nm deposit of aluminium as ohmic contact on p-type SiC. Electrical measurements show a bipolar behaviour, and very high sustainable forward current densities ≥ 3 kA.cm-2, preserving a low leakage current density in reverse bias. These measurements were obtained on structures without any passivation and no edge termination.


2021 ◽  
Author(s):  
Mikhail Basov

The small silicon chip of Schottky diode (0.8x0.8x0.4 mm<sup>3</sup>) with planar arrangement of electrodes (chip PSD) as temperature sensor, which functions under the operating conditions of pressure sensor, was developed. The forward I-V characteristic of chip PSD is determined by potential barrier between Mo and n-Si (N<sub>D</sub> = 3 × 10<sup>15</sup> cm<sup>-3</sup>). Forward voltage U<sub>F</sub> = 208 ± 6 mV and temperature coefficient TC = -1.635 ± 0.015 mV/⁰C (with linearity k<sub>T</sub> <0.4% for temperature range of -65 to +85 ⁰C) at supply current I<sub>F</sub> = 1 mA is achieved. The reverse I-V characteristic has high breakdown voltage U<sub>BR</sub> > 85 V and low leakage current I<sub>L</sub> < 5 μA at 25 ⁰C and I<sub>L</sub> < 130 μA at 85 ⁰C (U<sub>R</sub> = 20 V) because chip PSD contains the structure of two p-type guard rings along the anode perimeter. The application of PSD chip for wider temperature range from -65 to +115 ⁰C is proved. The separate chip PSD of temperature sensor located at a distance of less than 1.5 mm from the pressure sensor chip. The PSD chip transmits input data for temperature compensation of pressure sensor errors by ASIC and for direct temperature measurement.


2000 ◽  
Vol 657 ◽  
Author(s):  
Eivind Lund ◽  
Terje G. Finstad

ABSTRACTWe have performed new measurements of the temperature and doping dependency of the piezoresistive effect in p-type silicon. Piezoresistivity is one of the most common sensing principles of micro-electro-mechanical-systems (MEMS). Our measurements are performed in a specially designed setup based on the well-known 4 point bending technique. The samples are beams of full wafer thickness. To minimize leakage currents and to obtain uniform doping profiles, we have used SIMOX (Separation by IMplantation of OXygen) substrates with resistors defined in an epitaxial layer. Spreading resistance measurements show that the doping profiles are uniform with depth, while measurements of leakage current versus temperature indicate low leakage current. In this paper we present results for the doping concentration range from 1×1017 – 1×1020 cm−3 and the temperature range from –30 to 150 degrees Celsius. The results show a doping dependency of piezoresistivity well described by the current models. The measurements of the temperature dependency of the coefficients of piezoresistivity are compared to a linear model with a negative temperature coefficient whose absolute value decreases with increasing doping.


2006 ◽  
Vol 45 (No. 11) ◽  
pp. L319-L321 ◽  
Author(s):  
Norio Tsuyukuchi ◽  
Kentaro Nagamatsu ◽  
Yoshikazu Hirose ◽  
Motoaki Iwaya ◽  
Satoshi Kamiyama ◽  
...  

2005 ◽  
Vol 483-485 ◽  
pp. 953-956 ◽  
Author(s):  
Tetsuya Hayashi ◽  
Hideaki Tanaka ◽  
Yoshio Shimoida ◽  
Satoshi Tanimoto ◽  
Masakatsu Hoshi

We demonstrate a new high-voltage p+ Si/n- 4H-SiC heterojunction diode (HJD) by numerical simulation and experimental results. This HJD is expected to display good reverse recovery because of unipolar action similar to that of a SiC Schottky barrier diode (SBD) when forward biased. The blocking voltage of the HJD is almost equal to the ideal level in the drift region of n- 4H-SiC. In addition, the HJD has the potential for a lower reverse leakage current compared with the SBD. A HJD was fabricated with p+-type polycrystalline silicon on an n--type epitaxial layer of 4H-SiC. Measured reverse blocking voltage was 1600 V with low leakage current. Switching characteristics of the fabricated HJD showed nearly zero reverse recovery with an inductive load circuit.


2013 ◽  
Vol 1561 ◽  
Author(s):  
Shojan P. Pavunny ◽  
Pankaj Misra ◽  
Reji Thomas ◽  
Ashok Kumar ◽  
James F. Scott ◽  
...  

ABSTRACTA detailed analysis of leakage current density-gate voltage measurements of gate stacks composed of PLD grown ultra thin films of LaGdO3 (LGO) on p-type silicon substrates with 8.4 Å EOT is presented. Temperature dependent leakage measurements revealed that forward bias current was dominated by Schottky emission over trap assisted tunneling below 1.2 MV/cm and quantum mechanical tunneling above this field. The physical origin of the reverse bias current was found to be a combination of Schottky emission and trap assisted tunneling. Low leakage current densities in the range from 2.3×10-3 to 29×10-3 A/cm2 were recorded for films with EOT from 1.8 to 0.8 nm, that are at least four or more orders below the ITRS specifications and its SiO2 competitors.


2007 ◽  
Vol 336-338 ◽  
pp. 21-23
Author(s):  
Qiu Sun ◽  
Ying Song ◽  
Fu Ping Wang

The Pb(Zr0.52Ti0.48)O3 thin films with 0-2at.%Gd dopants (denoted as PGZT) were prepared on Pt/Ti/SiO2/Si substrates by a sol-gel technique and a rapid thermal annealing process. The structures of PGZT films were characterized and the ferroelectric properties such as P–V loop, C–V and I–V characteristics were investigated. Improved polarization (2Pr = 46.373 μC/cm2) and the low leakage current (J = 1.5×10-9 A/cm2 at the electric field of 400 kV/cm) were obtained in the PZT thin film with 1at.% Gd dopant, which was better than that of the pure PZT thin film (2Pr = 39.099 μC/cm2, J = 4.3×10-8A/cm2). With the Gd contents up to 2at.%, a decreased remanent polarization was found.


2021 ◽  
Author(s):  
Mikhail Basov

The small silicon chip of Schottky diode (0.8x0.8x0.4 mm<sup>3</sup>) with planar arrangement of electrodes (chip PSD) as temperature sensor, which functions under the operating conditions of pressure sensor, was developed. The forward I-V characteristic of chip PSD is determined by potential barrier between Mo and n-Si (N<sub>D</sub> = 3 × 10<sup>15</sup> cm<sup>-3</sup>). Forward voltage U<sub>F</sub> = 208 ± 6 mV and temperature coefficient TC = -1.635 ± 0.015 mV/⁰C (with linearity k<sub>T</sub> <0.4% for temperature range of -65 to +85 ⁰C) at supply current I<sub>F</sub> = 1 mA is achieved. The reverse I-V characteristic has high breakdown voltage U<sub>BR</sub> > 85 V and low leakage current I<sub>L</sub> < 5 μA at 25 ⁰C and I<sub>L</sub> < 130 μA at 85 ⁰C (U<sub>R</sub> = 20 V) because chip PSD contains the structure of two p-type guard rings along the anode perimeter. The application of PSD chip for wider temperature range from -65 to +115 ⁰C is proved. The separate chip PSD of temperature sensor located at a distance of less than 1.5 mm from the pressure sensor chip. The PSD chip transmits input data for temperature compensation of pressure sensor errors by ASIC and for direct temperature measurement.


Sign in / Sign up

Export Citation Format

Share Document