Electrical Characterization of Large Area 800 V Enhancement-Mode SiC VJFETs for High Temperature Applications

2009 ◽  
Vol 615-617 ◽  
pp. 715-718 ◽  
Author(s):  
Andrew Ritenour ◽  
Volodymyr Bondarenko ◽  
Robin L. Kelley ◽  
David C. Sheridan
Keyword(s):  
High Temperature ◽  
Elevated Temperature ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Electrical Characterization ◽  
Saturation Current ◽  
Large Area ◽  
Enhancement Mode ◽  
High Temperature Operation

Prototype 800 V, 47 A enhancement-mode SiC VJFETs have been developed for high temperature operation (250 °C). With an active area of 23 mm2 and target threshold voltage of +1.25 V, these devices exhibited a 28 m room temperature on-resistance and excellent blocking characteristics at elevated temperature. With improved device packaging, on-resistance and saturation current values of 15 m and 100 A, respectively, are achievable.

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

Normally-off GaN MOSFETs on Silicon Substrates with High-temperature Operation

2009 ◽  
Vol 1202 ◽  
Author(s):  
Hiroshi Kambayashi ◽  
Yuki Niiyama ◽  
Takehiko Nomura ◽  
Masayuki Iwami ◽  
yoshihiro Satoh ◽  
...  
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Silicon Substrates ◽  
Enhancement Mode ◽  
Threshold Voltages ◽  
Source Voltage ◽  
Gan Hfet ◽  
Output Characteristics ◽  
High Temperature Operation ◽  
State Resistance

AbstractWe have demonstrated enhancement-mode n-channel gallium nitride (GaN) MOSFETs on Si (111) substrates with high-temperature operation up to 300 °C. The GaN MOSFETs have good normally-off operation with the threshold voltages of +2.7 V. The MOSFET exhibits good output characteristics from room temperature to 300 °C. The leakage current at 300°C is less than 100 pA/mm at the drain-to-source voltage of 0.1 V. The on-state resistance of MOSFET at 300°C is about 1.5 times as high as that at room temperature. These results indicate that GaN MOSFET is suitable for high-temperature operation compared with AlGaN/GaN HFET.

300C Capable Digital Integrated Circuits in SiC Technology

2012 ◽  
Vol 717-720 ◽  
pp. 1261-1264 ◽  
Author(s):  
Amita Patil ◽  
Naresh Rao ◽  
Vinayak Tilak
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Elevated Temperature ◽  
Integrated Circuits ◽  
Room Temperature ◽  
Continuous Operation ◽  
Shift Register ◽  
Digital Integrated Circuits ◽  
Enhancement Mode

This paper pertains to development of high temperature capable digital integrated circuits in n-channel, enhancement-mode Silicon Carbide (SiC) MOS technology. Among the circuits developed in this work are data latch, flip flops, 4-bit shift register and ripple counter. All circuits are functional from room temperature up to 300C without any notable degradation in performance at elevated temperature. The 4-bit counter demonstrated stable behavior for over 500 hours of continuous operation at 300C.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Electrical Characterization of InAs/(GaIn)Sb Infrared Superlattice Photodiodes for the 8 to 12νm Range

1999 ◽  
Vol 607 ◽  
Author(s):  
L. Bürkle ◽  
F. Fuchs ◽  
R. Kiefer ◽  
W. Pletschen ◽  
R. E. Sah ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Cutoff Wavelength ◽  
Saturation Current ◽  
Diffusion Limited ◽  
Saturation Current Density ◽  
Out Of Plane ◽  
Reverse Saturation Current ◽  
The Magnetic Field ◽  
Diode Current

AbstractInAs/(GaIn)Sb superlattice photodiodes with a cutoff wavelength of 8.711μm show adynamic impedance of R0A= 1.5 kωcm2at 77 K and a responsivity of 2 A/W, corresponding to a detectivity of D*= 1 x 1012 cmv√Hz/W. Diffusion limited performance is observed above 100 K. At lower temperatures the diodesare limited by generation-recombination currents. An analysis of the influence of different diode sidewall passivations on the surface contribution to the diode leakage current is presented. The out-of-plane electron mobility as well as the relative contributions of the electron and hole diffusion currents to the diode current were determined by a measurement of the magnetic field dependence of the reverse saturation current density of the diodes

scholarly journals Synthesis and electrical characterization of Ca2Nd4Ti6O20 ceramics

2016 ◽  
Vol 34 (1) ◽  
pp. 164-168
Author(s):  
Raz Muhammad ◽  
Muhammad Uzair ◽  
M. Javid Iqbal ◽  
M. Jawad Khan ◽  
Yaseen Iqbal ◽  
...  
Keyword(s):  
Activation Energy ◽  
Dielectric Constant ◽  
Room Temperature ◽  
Sol Gel ◽  
Electrical Characterization ◽  
Sintered Sample ◽  
First Time ◽  
Alkoxide Precursors ◽  
Room Temperature Dielectric Constant

AbstractCa2Nd4Ti6O20, a layered perov skite structured material was synthesized via a chemical (citrate sol-gel) route for the first time using nitrates and alkoxide precursors. Phase analysis of a sample sintered at 1625 °C revealed the formation of an orthorhombic (Pbn21) symmetry. The microstructure of the sample after sintering comprised rod-shaped grains of a size of 1.5 to 6.5µm. The room temperature dielectric constant of the sintered sample was 38 at 100 kHz. The remnant polarization (Pr) and the coercive field (Ec) were about 400 μC/cm2 and 8.4 kV/cm, respectively. Impedance spectroscopy revealed that the capacitance (13.7 pF) and activation energy (1.39 eV) of the grain boundary was greater than the capacitance (5.7 pF) and activation energy (1.13 eV) of the grain.

Electrical characterization of room temperature humidity sensors in La0.8Sr0.2Fe1−xCuxO3 (x=0, 0.05, 0.10)

2012 ◽  
Vol 38 (4) ◽  
pp. 2865-2872 ◽  
Author(s):  
A. Cavalieri ◽  
T. Caronna ◽  
I. Natali Sora ◽  
J.M. Tulliani
Keyword(s):  
Room Temperature ◽  
Electrical Characterization ◽  
Humidity Sensors

Three-Dimensional Numerical Analysis for Bolted Flange Joints Considering Effect of Creep

2018 ◽  
Author(s):  
Lewen Bi ◽  
Lanzhu Zhang
Keyword(s):  
High Temperature ◽  
Elevated Temperature ◽  
Numerical Analysis ◽  
Yield Strength ◽  
Room Temperature ◽  
Three Dimensional ◽  
Short Term ◽  
Flange Connection ◽  
Petroleum Chemical ◽  
Bolted Flange

Bolted flange joints are widely used in petroleum, chemical, nuclear and power industries, etc. With more and more devices are used at high temperature, the performance of flange connections becomes more complex, especially with creep of different components in flange connection. At elevated temperature, with the loss of bolt force and gasket force due to creep, the joints are prone to leak. Based on this, this paper analyzed the relaxation of bolt force at elevated temperature due to creep of bolt, flange and gasket separately and simultaneously. Besides, the influence of different initial installation stress of bolts was also studied. The results showed bolted flange joints relaxed due to gasket creep during early short term service. However, contribution of bolt and flange creep became more and more significant with the extension of time. With considering the creep of bolt, flange and gasket simultaneously, 50% to 60% of the bolt material yield strength at room temperature was recommended as the bolt initial installation stress for the joint case studied in this paper.

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