Performance of 60 A, 1200 V 4H-SiC DMOSFETs

2009 ◽  
Vol 615-617 ◽  
pp. 749-752 ◽  
Author(s):  
Brett A. Hull ◽  
Charlotte Jonas ◽  
Sei Hyung Ryu ◽  
Mrinal K. Das ◽  
Michael J. O'Loughlin ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Power Dissipation ◽  
Avalanche Breakdown ◽  
Large Area ◽  
Leakage Currents ◽  
Inductive Load ◽  
Turn On ◽  
Load Circuit

Large area (8 mm x 7 mm) 1200 V 4H-SiC DMOSFETs with a specific on-resistance as low as 9 m•cm2 (at VGS = 20 V) able to conduct 60 A at a power dissipation of 200 W/cm2 are presented. On-resistance is fairly stable with temperature, increasing from 11.5 m•cm2 (at VGS = 15 V) at 25°C to 14 m•cm2 at 150°C. The DMOSFETs exhibit avalanche breakdown at 1600 V with the gate shorted to the source, although sub-breakdown leakage currents up to 50 A are observed at 1200 V and 200°C due to the threshold voltage lowering with temperature. When switched with a clamped inductive load circuit from 65 A conducting to 750 V blocking, the turn-on and turn-off energies at 150°C were less than 4.5 mJ.

High-Voltage Stacked Diode Package

2015 ◽  
Vol 2015 (1) ◽  
pp. 000225-000230 ◽  
Author(s):  
Lauren Boteler ◽  
Alexandra Rodriguez ◽  
Miguel Hinojosa ◽  
Damian Urciuoli
Keyword(s):  
Silicon Carbide ◽  
High Voltage ◽  
Recovery Time ◽  
Load Test ◽  
Avalanche Breakdown ◽  
Electric Force ◽  
Inductive Load ◽  
Turn On ◽  
Series Configuration ◽  
Reverse Recovery Time

The Army is moving to a more electric force with a number of high-voltage applications. To support this transition, there have been efforts to develop high voltage (15–30 kV) single-die 4H-silicon carbide (SiC) bipolar switches and diodes. However, packaging these high-voltage devices has proven to be challenging since standard packaging methods cannot withstand the high voltages in a compact form. Therefore, this work aims to develop a compact prototype package with improved size, weight, and power density by stacking diodes. The stacked diode approach allows elimination of almost half of the wirebonds, reduces the board size by 45%, and reduces the package inductance. A module has been designed, fabricated, and tested which is the first 30 kV module reported in the literature to stack two high-voltage diodes in a series configuration. The package has a number of features specific to high-voltage packaging including (1) two fins that extend the perimeter of the package to mitigate shorting, and (2) all the leads were designed with rounded corners to minimize voltage crowding. Hi-pot tests were performed on the unpopulated package and showed the package can withstand 30 kV without breaking down. The completed package with the stacked diodes showed avalanche breakdown occurring at 29 kV. The complete package was then compared to an equivalent discrete diode module and showed a 10X reduction in size. During a clamped-inductive load test the stacked diodes showed lower parasitic capacitance, faster reverse recovery time, and lower turn on energy as compared to the discrete diode packages.

Superior Short Circuit Performance of 1.2kV SiC JBSFETs Compared to 1.2kV SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 797-800 ◽  
Author(s):  
Ajit Kanale ◽  
Ki Jeong Han ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya
Keyword(s):  
High Temperature ◽  
Short Circuit ◽  
Switching Loss ◽  
Switching Circuit ◽  
Inductive Load ◽  
Circuit Performance ◽  
Switching Performance ◽  
Turn On ◽  
Switching Losses ◽  
High Side

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.

Evaluation of SiC Stack Cascode for 200°C Operations

2014 ◽  
Vol 778-780 ◽  
pp. 879-882 ◽  
Author(s):  
Xue Qing Li ◽  
Petre Alexandrov ◽  
John Hostetler ◽  
Anup Bhalla
Keyword(s):  
Dynamic Characteristics ◽  
Threshold Voltage ◽  
Load Condition ◽  
Experimental Results ◽  
Reliability Test ◽  
Inductive Load ◽  
Static And Dynamic Characteristics

This paper evaluates the static and dynamic characteristics of a 1.2kV SiC stack-cascode at junction temperatures (Tj) up to 200°C. The experimental results show that, at Tj = 200°C, the SiC stack-cascode can be switched stably under a 600V-17A inductive load condition and can withstand an avalanche current of 13A for 9μs (Eav = 116mJ) for a 1.5mH load inductor. The SiC stack-cascode has no degradation in on-resistance, threshold voltage and blocking characteristics after 80 hours HTRB reliability test at 200°C ambient. These promising experimental results indicate the possibility of the SiC stack-cascode for reliable 200°C operations.

Fabricaton Ofactive Devices and Logic Gates on Fibers

2003 ◽  
Vol 769 ◽  
Author(s):  
YongWoo Choi ◽  
Ioannis Kymissis ◽  
Annie Wang ◽  
Akintunde I. Akinwande
Keyword(s):  
Threshold Voltage ◽  
Electronic Structures ◽  
Low Cost ◽  
Logic Gates ◽  
Wearable Electronics ◽  
Drain Voltage ◽  
Large Area ◽  
Active Devices ◽  
P Type ◽  
A Current

AbstractTextiles are a suitable substrate for large area, flexible and wearable electronics because of their excellent flexibility, mechanical properties and low cost manufacturability. The ability to fabricate active devices on fiber is a key step for achieving large area and flexible electronic structures. We fabricated transistors and inverters with a-Si film and pentacene film on Kapton film and cut them into fibers. The a-Si TFT showed a threshold voltage of 8.5 V and on/off ratio of 103 at a drain voltage of 10 V. These are similar to the characteristics of a TFT fabricated on a glass substrate at the same time. The maximum gain of the inverter with an enhancement n-type load was 6.45 at a drain voltage of 10 V. The pentacene OTFT showed a threshold voltage of -8 V and on/off ratio of 103 at a drain voltage of -30 V. The inverter with a depletion p-type load showed a voltage inversion but the inversion occurred at the wrong voltage. The antifuse was successfully programmed with a voltage pulse and also a current pulse. The resistance decreased from 10 GΩ to 2 kΩ after the programming.

Fabrication of 2.5kV 4H-SiC PiN Diodes with High Energy Implantation (>12MeV) of Al+ and B+

2018 ◽  
Vol 924 ◽  
pp. 573-576 ◽  
Author(s):  
Reza Ghandi ◽  
Peter Losee ◽  
Alexander Bolotnikov ◽  
David Lilienfeld
Keyword(s):  
Reverse Bias ◽  
High Energy ◽  
Avalanche Breakdown ◽  
Leakage Currents ◽  
Pin Diodes ◽  
Minimal Defect ◽  
Low Leakage ◽  
Pn Junction ◽  
Defect Sites

In this work, >2kV PiN diodes with >10um deep implant of B+ and 6um deep implant of Al+ have been fabricated to evaluate the quality of resulting pn junction after high-energy implantation. Acceptable low leakage currents at reverse bias and stable avalanche breakdown were observed for high energy implanted diodes (HEI-diodes) when compared to No-HEI-diodes that suggests minimal defect sites present after activation anneal.

Design and Gate Drive Considerations for Epitaxial 1.2 kV Buried Grid N-on and N-off JFETs for Operation at 250°C

2010 ◽  
Vol 645-648 ◽  
pp. 961-964 ◽  
Author(s):  
Jang Kwon Lim ◽  
Mietek Bakowski ◽  
Hans Peter Nee
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Channel Length ◽  
Channel Width ◽  
Temperature Range ◽  
Turn On ◽  
Switching Losses ◽  
Order Of Magnitude ◽  
Gate Resistance

The 1.2 kV 4H-SiC buried-grid vertical JFET structures with Normally-on (N-on) and Normally-off (N-off) design were investigated by simulations. The conduction and switching properties were determined in the temperature range from -50°C to 250°C. In this paper, the characteristics of the N-on designs with threshold voltage (Vth) of -50 V and -10 V are compared with the N-off design (Vth=0). The presented data are for devices with the same channel length at 250°C. The results show that the on-resistance (Ron) decreases with increasing channel doping concentration and decreasing channel width. The presented turn-on, Eon, and turn-off, Eoff, energies per pulse are calculated under the switching conditions 100 A/cm2 and 600 V with a gate resistance of Rg=1 . For the two N-on designs the total switching losses, Esw=Eon+Eoff, differ less than 30% with Wch 0.7 m. With Wch=0.5 m the switching losses of N-off design are almost one order of magnitude higher than those of the N-on design with Vth = -50 V.

Evaluation of 4H–SiC DMOSFETs for High–Power Electronics Applications

2008 ◽  
Vol 600-603 ◽  
pp. 1135-1138 ◽  
Author(s):  
Ronald Green ◽  
Aderinto Ogunniyi ◽  
Dimeji Ibitayo ◽  
Gail Koebke ◽  
Mark Morgenstern ◽  
...  
Keyword(s):  
High Voltage ◽  
Voltage Drop ◽  
Drain Current ◽  
High Temperature Stress ◽  
Large Area ◽  
Inductive Load ◽  
Current Sharing ◽  
Load Tests ◽  
Source Voltage ◽  
Increasing Temperature

In this paper, large area (0.18cm2) SiC DMOSFETs with 1.2 kV and 20 A rating are evaluated for power electronic switching applications. A drain-to-source voltage drop VDS of 2 V at a forward drain current of 20 A (JD = 110 A/cm2) was obtained and a specific on-resistance of 18 mΩ-cm2 was extracted at room temperature. The device on-resistance was measured up to 150°C and initially decreases with increasing temperature, but remains relatively flat over the entire temperature range, demonstrating stable device behavior. High voltage blocking of 1.2 kV between 25°C and 150°C is also demonstrated with a gate-to-source voltage VGS = 0 V. The drain leakage current under reverse bias and high temperature stress is shown to increase from 10 μA at 25°C to 27 μA at 150°C while maintaining the full blocking rating of the device. Experimental results from double-pulse clamped inductive load tests are presented demonstrating fast high voltage and high current switching capability. High voltage resistive-switching measurements on parallel connected SiC DMOSFETs were performed with VDS having rise and fall times of 49 and 74 ns respectively. Thermal camera images taken of parallel connected DMOSFET die during repetitive switching operation with VDS = 420 V, IDS = 25 A and a 40% duty cycle shows a 2°C difference in die temperature, which suggests even current sharing and temperature stable device operation.

scholarly journals Pentacene Active Channel Layers Prepared by Spin-Coating and Vacuum Evaporation Using Soluble Precursors for OFET Applications

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Shizuyasu Ochiai ◽  
Kumar Palanisamy ◽  
Santhakumar Kannappan ◽  
Paik-Kyun Shin
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Spin Coating ◽  
Dielectric Layer ◽  
Gate Dielectric ◽  
Low Cost ◽  
Vacuum Evaporation ◽  
Large Area ◽  
Process Technology ◽  
Active Channel

Pentacene OFETs of bottom-gate/bottom-contact were fabricated with three types of pentacene organic semiconductors and cross linked Poly(4-vinylphenol) or polycarbonate as gate dielectric layer. Two different processes were used to prepare the pentacene active channel layers: (1) spin-coating on dielectric layer using two different soluble pentacene precursors of SAP and DMP; (2) vacuum evaporation on PC insulator. X-ray diffraction studies revealed coexistence of thin film and bulk phase of pentacene from SAP and thin film phase of pentacene from DMP precursors. The field effect mobility of 0.031 cm2/Vs and threshold voltage of −12.5 V was obtained from OFETs fabricated from SAP precursor, however, the pentacene OFETs from DMP under same preparation yielded high mobility of 0.09 cm2/Vs and threshold value decreased to −5 V. It reflects that the mixed phase films had carrier mobilities inferior to films consisting solely of single phase. For comparison, we have also fabricated pentacene OFETs by vacuum evaporation on polycarbonate as the gate dielectric and obtained charge carrier mobilities as large as 0.62 cm2/Vs and threshold voltage of −8.5 V. We demonstrated that the spin-coated pentacene using soluble pentacene precursors could be alternative process technology for low cost, large area and low temperature fabrication of OFETs.

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