Impact of Channel Mobility Improvement Using Boron Diffusion on Different Power MOSFETs Voltage Classes

2017 ◽  
Vol 897 ◽  
pp. 537-540
Author(s):  
Victor Soler ◽  
Maria Cabello ◽  
Maxime Berthou ◽  
Josep Montserrat ◽  
José Rebollo ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Pin Diode ◽  
Boron Diffusion ◽  
Oxide Formation ◽  
Interface Quality ◽  
Channel Mobility ◽  
Power Mosfets ◽  
The Impact ◽  
Effective Channel ◽  
Drift Layer

SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO2/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

Design and Process Issues for Silicon Carbide Power DiMOSFETS

2000 ◽  
Vol 640 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Anant K. Agarwal ◽  
Nelson S. Saks ◽  
Mrinal K. Das ◽  
Lori A. Lipkin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Structure ◽  
Channel Mobility ◽  
Power Mosfets ◽  
Buried Channel ◽  
P Type ◽  
Very High ◽  
Effective Channel

ABSTRACTThis paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (EC) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μeff) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μeff. NO anneal, which was reported to be very effective in increasing the μeff of SiC MOSFETS in p-type epilayers, did not produce reasonable μeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μeff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.

High Temperature Rapid Thermal Oxidation and Nitridation of 4H-SiC in Diluted N2O and NO Ambient

2005 ◽  
Vol 483-485 ◽  
pp. 669-672 ◽  
Author(s):  
Ryouji Kosugi ◽  
Kenji Fukuda ◽  
Kazuo Arai
Keyword(s):  
High Temperature ◽  
Gate Oxide ◽  
Process Time ◽  
Oxide Formation ◽  
Mos Capacitor ◽  
Channel Mobility ◽  
Oxidation Rates ◽  
Capacitance Voltage ◽  
Total Process ◽  
Ambient Gases

A high temperature rapid thermal processing (HT-RTP) above 1400oC was investigated for use in the gate oxide formation of 4H-SiC by a cold-wall oxidation furnace. The gate oxide film of ~50nm can be formed for several minutes in the oxidizing atmospheres such as N2O and O2, where the oxidation rates were 8-10nm/min. After the initial oxide formation, the HT-RTPs in various ambient gases were conducted, and the dependences of their MOS interface properties on the gases were evaluated by a capacitance-voltage (CV) measurement. Based on the results, the process sequence of gate oxidation was determined as follows; the initial oxide was formed by the HT-RTO (oxidation) in N2O or in O2 with subsequent post annealing in Ar ambient, and then the HT-RTN (nitridation) in NO was conducted. The total process time becomes 20-50min. The interface trap density (Dit) of fabricated MOS capacitor shows 3-5x1011cm-2eV-1 at Ec-E~0.2eV. The field-effect channel mobility of fabricated 4H-SiC lateral MOSFETs was ~30cm2/Vs.

The Characteristics of MOSFETs Fabricated on the Trench Sidewalls of Various Faces Using 4H-SiC (11-20) Substrates

2006 ◽  
Vol 527-529 ◽  
pp. 1297-1300
Author(s):  
Hiroyuki Fujisawa ◽  
Takashi Tsuji ◽  
Masaharu Nishiura
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Effective Channel

This paper reports the channel mobilities of MOSFETs formed on the trench sidewalls with different crystal faces including (0001), (000-1), (1-100) and (0-33-8) using 4H-SiC (11-20) substrates. Deposited poly-Si was oxidized in wet ambient to form the gate oxide, and annealed in N2O (10%) ambient. The order of drain current of trench sidewall MOSFETs was (0-33-8) > (1-100) > (000-1) = (0001). We could gain comparatively high channel mobility on the (0-33-8) face. The maximum effective channel mobility (μeff) was 35cm2/Vs, and μeff at 2.5MV/cm was 29 cm2/Vs on the (0-33-8) face.

Proton and Electron Irradiation in Oxynitrided Gate 4H-SiC MOSFET: A Recent Open Issue

2015 ◽  
Vol 821-823 ◽  
pp. 667-672 ◽  
Author(s):  
Matthieu Florentin ◽  
Mihaela Alexandru ◽  
Aurore Constant ◽  
Philippe Michel ◽  
Josep Montserrat ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Special Focus ◽  
Channel Mobility ◽  
Mos Devices ◽  
Post Annealing ◽  
Military Applications ◽  
Open Issue ◽  
Effective Channel ◽  
Open Issues

Long-term degradation of MOS devices has to be avoided in different harsh irradiated environments, especially for aerospace or military applications. In this paper, an overview of the irradiation experiments recently performed on 4H-SiC MOSFETs having an oxynitrided gate oxide is given, with a special focus on the threshold voltage and the effective channel mobility drifts. The general mechanisms taking place during irradiation and post-annealing treatments are described. Finally, new open issues recently observed by performing the temperature measurement on irradiated MOSFETs will be introduced and discussed.

Improving 5V Digital 4H-SiC CMOS ICs for Operating at 400°C Using PMOS Channel Implantation

2019 ◽  
Vol 963 ◽  
pp. 827-831 ◽  
Author(s):  
Matthaeus Albrecht ◽  
Tobias Erlbacher ◽  
Anton Bauer ◽  
Lothar Frey
Keyword(s):  
Power Supply ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Implantation Dose ◽  
Channel Mobility ◽  
Propagation Delay Time ◽  
The Impact ◽  
Channel Properties ◽  
Input Level ◽  
Effective Channel

In this work, the impact of a shallow aluminum channel implantation on the channel properties of SiC p-MOSFETs and digital SiC CMOS devices is investigated. For this purpose, p-MOSFETs, CMOS inverters and ring oscillators with different channel implantation doses were fabricated and electrically characterized. The threshold voltage of the resulting p-MOSFETs was shifted from-5 V to-3.6 V whereas the effective channel mobility was slightly decreased from 11.8 cm2/Vs to 10.2 cm2/Vs for a p-MOSFET channel implantation dose of 2∙1013 cm-2 compared to the non-implanted channel. The resulting p-MOSFETs enable SiC CMOS logic circuits to operate with a 5 V power supply and to satisfy 5 V TTL input level specification over the whole temperature range of 25°C to 400°C. Furthermore the propagation delay time of inverters was reduced by 80% at 25°C and 40% at 400°C compared to inverters without p-MOSFET channel implantation.

scholarly journals Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs lifetime by Reliability Tests

Sensors ◽  
2021 ◽  
Vol 21 (16) ◽  
pp. 5627
Author(s):  
Fabio Principato ◽  
Giuseppe Allegra ◽  
Corrado Cappello ◽  
Olivier Crepel ◽  
Nicola Nicosia ◽  
...  
Keyword(s):  
High Temperature ◽  
Neutron Irradiation ◽  
Neutron Fluence ◽  
Electrical Characterization ◽  
Gate Oxide ◽  
Power Devices ◽  
Electrical Parameters ◽  
Power Mosfets ◽  
The Impact ◽  
Dc Characterization

High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non irradiated devices and those which survived to the neutron irradiation tests, with neutron fluence up to 2× 1011 (n/cm2). Electrical characterization performed pre and post-irradiation on different part number of power devices (Si, SiC MOSFETs and IGBTs) which survived to neutron irradiation tests does not show alteration of the data-sheet electrical parameters due to neutron interaction with the device.

Influence of Metallization Annealing on Channel Mobility in 4H-SiC MOSFET on Carbon Face

2008 ◽  
Vol 600-603 ◽  
pp. 675-678 ◽  
Author(s):  
Shinsuke Harada ◽  
Makoto Kato ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda ◽  
Kazuo Arai
Keyword(s):  
Ohmic Contact ◽  
Gate Oxide ◽  
Wet Oxidation ◽  
Hydrogen Annealing ◽  
Channel Mobility ◽  
Power Mosfets ◽  
Metallization Process

4H-SiC MOSFET on carbon face exhibits the high channel mobility when the gate oxide is formed by pyrogenic wet oxidation. However, this improvement is not proof against the metallization annealing which is indispensable in the fabrication of the SiC power MOSFETs. We develop the alternative metallization process suitable for the high channel mobility on the carbon face. The metallization annealing in hydrogen ambient has much effect to suppress the degradation of the channel mobility. The lateral MOSFET with the ohmic contact formed by hydrogen annealing exhibits the high channel mobility which is comparable to the channel mobility of the lateral MOSFET formed without metallization annealing.

Exploration of heavy ion irradiation effects on gate oxide reliability in power MOSFETs

1995 ◽  
Vol 35 (3) ◽  
pp. 603-608 ◽  
Author(s):  
S.R. Anderson ◽  
R.D. Schrimpf ◽  
K.F. Galloway ◽  
J.L. Titus
Keyword(s):  
Ion Irradiation ◽  
Gate Oxide ◽  
Heavy Ion ◽  
Irradiation Effects ◽  
Power Mosfets ◽  
Heavy Ion Irradiation ◽  
Oxide Reliability

Hydrogen Concentration Analysis in Pecvd and Rtcvd Silicon Nitride Thin Films and It's Impact on Device Performance

2001 ◽  
Vol 664 ◽  
Author(s):  
C. Y. Wang ◽  
E. H. Lim ◽  
H. Liu ◽  
J. L. Sudijono ◽  
T. C. Ang ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Threshold Voltage ◽  
Vapor Deposition ◽  
Gas Flow ◽  
Chemical Vapor ◽  
Gate Oxide ◽  
Nitride Film ◽  
Device Performance ◽  
Gas Flow Ratio ◽  
The Impact

ABSTRACTIn this paper the impact of the ESL (Etch Stop layer) nitride on the device performance especially the threshold voltage (Vt) has been studied. From SIMS analysis, it is found that different nitride gives different H concentration, [H] in the Gate oxide area, the higher [H] in the nitride film, the higher H in the Gate Oxide area and the lower the threshold voltage. It is also found that using TiSi instead of CoSi can help to stop the H from diffusing into Gate Oxide/channel area, resulting in a smaller threshold voltage drift for the device employed TiSi. Study to control the [H] in the nitride film is also carried out. In this paper, RBS, HFS and FTIR are used to analyze the composition changes of the SiN films prepared using Plasma enhanced Chemical Vapor deposition (PECVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) with different process parameters. Gas flow ratio, RF power and temperature are found to be the key factors that affect the composition and the H concentration in the film. It is found that the nearer the SiN composition to stoichiometric Si3N4, the lower the [H] in SiN film because there is no excess silicon or nitrogen to be bonded with H. However the lowest [H] in the SiN film is limited by temperature. The higher the process temperature the lower the [H] can be obtained in the SiN film and the nearer the composition to stoichiometric Si3N4.

The impact of F contamination induced by the process on the gate oxide reliability

1998 ◽  
Vol 38 (2) ◽  
pp. 255-258 ◽  
Author(s):  
G Ghidini ◽  
C Clementi ◽  
D Drera ◽  
F Maugain
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
The Impact
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