High Temperature Rapid Thermal Oxidation and Nitridation of 4H-SiC in Diluted N2O and NO Ambient

2005 ◽  
Vol 483-485 ◽  
pp. 669-672 ◽  
Author(s):  
Ryouji Kosugi ◽  
Kenji Fukuda ◽  
Kazuo Arai
Keyword(s):  
High Temperature ◽  
Gate Oxide ◽  
Process Time ◽  
Oxide Formation ◽  
Mos Capacitor ◽  
Channel Mobility ◽  
Oxidation Rates ◽  
Capacitance Voltage ◽  
Total Process ◽  
Ambient Gases

A high temperature rapid thermal processing (HT-RTP) above 1400oC was investigated for use in the gate oxide formation of 4H-SiC by a cold-wall oxidation furnace. The gate oxide film of ~50nm can be formed for several minutes in the oxidizing atmospheres such as N2O and O2, where the oxidation rates were 8-10nm/min. After the initial oxide formation, the HT-RTPs in various ambient gases were conducted, and the dependences of their MOS interface properties on the gases were evaluated by a capacitance-voltage (CV) measurement. Based on the results, the process sequence of gate oxidation was determined as follows; the initial oxide was formed by the HT-RTO (oxidation) in N2O or in O2 with subsequent post annealing in Ar ambient, and then the HT-RTN (nitridation) in NO was conducted. The total process time becomes 20-50min. The interface trap density (Dit) of fabricated MOS capacitor shows 3-5x1011cm-2eV-1 at Ec-E~0.2eV. The field-effect channel mobility of fabricated 4H-SiC lateral MOSFETs was ~30cm2/Vs.

Characterization of Large Area 4H-SiC and 6H-SiC Capacitive Devices at 600 °C

2012 ◽  
Vol 717-720 ◽  
pp. 1187-1189
Author(s):  
Ruby N. Ghosh ◽  
Reza Loloee
Keyword(s):  
High Temperature ◽  
Field Effect ◽  
Gate Oxide ◽  
Voltage Characteristic ◽  
Capacitive Sensors ◽  
Large Area ◽  
Signal Noise ◽  
Capacitance Voltage ◽  
Corrosive Environments

SiC based capacitive devices have the potential to operate in high temperature, chemically corrosive environments provided that the electrical integrity of the gate oxide and metallization can be maintained in these environments. We report on the performance of large area, up to 8 x 10-3 cm2, field-effect capacitive sensors fabricated on both the 4H and 6H polytypes at 600°C. Large area capacitors improve the signal/noise (S/N) ratio which is proportional to the slope of the capacitance-voltage characteristic. At 600 °C we obtain a S/N ~ 20. The device response is independent of polytype, either 4H or 6H-SiC. These results demonstrate the reliability of our field-effect structure, operating as a simple potentiometer at high temperature.

Impact of Channel Mobility Improvement Using Boron Diffusion on Different Power MOSFETs Voltage Classes

2017 ◽  
Vol 897 ◽  
pp. 537-540
Author(s):  
Victor Soler ◽  
Maria Cabello ◽  
Maxime Berthou ◽  
Josep Montserrat ◽  
José Rebollo ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Pin Diode ◽  
Boron Diffusion ◽  
Oxide Formation ◽  
Interface Quality ◽  
Channel Mobility ◽  
Power Mosfets ◽  
The Impact ◽  
Effective Channel ◽  
Drift Layer

SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO2/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

Improved Channel Mobility by Oxide Nitridation for N-Channel MOSFET on 3C-SiC(100)/Si

2016 ◽  
Vol 858 ◽  
pp. 667-670 ◽  
Author(s):  
Fan Li ◽  
Yogesh K. Sharma ◽  
M.R. Jennings ◽  
A. Pérez-Tomás ◽  
Vishal Ajit Shah ◽  
...  
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Oxidation Temperature ◽  
Channel Mobility ◽  
Si Substrates ◽  
Nitridation Process ◽  
Long Channel

In this work we studied the gate oxidation temperature and nitridation influences on the resultant 3C-SiC MOSFET forward characteristics. Conventional long channel lateral MOSFETs were fabricated on 3C-SiC(100) epilayers grown on Si substrates using five different oxidation process. Both room temperature and high temperature (up to 500K) forward IV performance were characterised, and channel mobility as high as 90cm2/V.s was obtained for devices with nitrided gate oxide, considerable higher than the ones without nitridation process (~70 cm2/V.s).

Study of the Post-Oxidation-Annealing (POA) Process on Deposited High-Temperature Oxide (HTO) Layers as Gate Dielectric in SiC MOSFET

2019 ◽  
Vol 963 ◽  
pp. 456-459
Author(s):  
Andrea Severino ◽  
Nicolò Piluso ◽  
Maria Ausilia di Stefano ◽  
Francesco Cordiano ◽  
Marco Camalleri ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectric ◽  
Gate Oxide ◽  
Oxide Semiconductor ◽  
Semiconductor Interface ◽  
Channel Mobility ◽  
A Value ◽  
High Temperature Oxide ◽  
Order Of Magnitude ◽  
Temperature Oxide

In the development of SiC MOSFETs, further improvements are ongoing to improve device performances. One of the critical part at the device level is the gate oxide/semiconductor interface, being the gate oxide a standard SiO2 layer. This work is focused on the investigation of the effect of post oxidation annealing process (POA) carried out after the deposition of high-temperature oxide (HTO) layer used for dielectric gate formation by using NO and N2O gasses. The variation of Dit by applying the POA in N2O is considerable with respect to the as-deposited oxide layer as the density is reduced of about two order of magnitude. A further reduction of interface trap density from 2.3×1010 to 8.5×109 traps/cm2 has been observed when NO POA process was applied. Full vertical power MOSFETs were also analyzed in order to measure the channel mobility of the device. Channel mobility has been seen to raise its value from 45 cm2/Vs to a value of about 62 cm2/Vs when NO-based POA process was performed. NO-based POA process results in a much more effective interface at device level.

High-Mobility SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate Stack

2018 ◽  
Vol 924 ◽  
pp. 494-497 ◽  
Author(s):  
Jesus Urresti ◽  
Faiz Arith ◽  
Konstantin Vassilevski ◽  
Amit Kumar Tiwari ◽  
Sarah Olsen ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
High Mobility ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Stack ◽  
Mos Capacitors ◽  
Channel Mobility

We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (DIT) at the SiC/SiO2interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm2·V-1·s-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the DITand channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

Highly Stable Ir-Ta-O Electrode for Ferroelectric Material Deposition

2000 ◽  
Vol 655 ◽  
Author(s):  
Fengyan Zhang ◽  
Sheng Teng Hsu ◽  
Jer-shen Maa ◽  
Yoshi Ono ◽  
Ying Hong ◽  
...  
Keyword(s):  
High Temperature ◽  
Bottom Electrode ◽  
Temperature Stability ◽  
Gate Oxide ◽  
Ferroelectric Material ◽  
High Temperature Stability ◽  
Material Deposition ◽  
Long Time ◽  
The Stability ◽  
Thin Gate Oxide

AbstractIr-Ta-O composite bottom electrode has extraordinary high temperature stability. It can maintain good conductivity and integrity even after 5min annealing at 1000 °C in oxygen ambient. The thermal stability of Ir-Ta-O on different substrates has been studied. It shows that Ir-Ta-O is also very stable on Si and SiO2 substrates. No hillock formation and peelings of the bottom electrode were observed after high temperature and long time annealing in O2 ambient. SEM, TEM, XRD, and AES have been used to characterize the Ir-Ta-O film and the interfaces between Ir-Ta-O bottom electrode and Si or SiO2 substrate. The composition and conductivity changes of the electrode during oxygen ambient annealing and the interdiffusion issue will be discussed. Furthermore, Ir-Ta-O/SiO2/Si capacitor with 30Å gate oxide was fabricated and the C-V and I-V characteristics were measured to confirm the stability of Ir-Ta-O on thin gate oxide.

Process Optimisation for 4H-SiC MOSFET Applications

2006 ◽  
Vol 527-529 ◽  
pp. 1051-1054 ◽  
Author(s):  
Caroline Blanc ◽  
Dominique Tournier ◽  
Phillippe Godignon ◽  
D.J. Brink ◽  
Véronique Soulière ◽  
...  
Keyword(s):  
Field Effect ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Process Optimisation ◽  
Field Effect Mobility ◽  
Oxide Formation ◽  
Step Procedure ◽  
P Type ◽  
Peak Value ◽  
Gas Precursor

We report on 4H-SiC MOSFET devices implemented on p-type <11-20>-oriented epitaxial layers, using a two-step procedure for gate oxide formation. First is a thin, dry, thermal SiO2 layer grown at 1050°C for 1 hour. Next, is a thick (50 nm) layer of complementary oxide deposited by PECVD using TEOS as gas precursor. With respect to the standard thermal oxidation process, this results in much improvement of the field effect mobility. For the best samples, we find a peak value in the range of 330 cm2/Vs while, on the full wafer, an average mobility of about 160 cm2/Vs is found. Up to now, this is one of the best results ever reported for 4H-SiC MOSFETs.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

Thermal Process Evaluation of Analogue Shrimp Product (ASP) from Lizard Fish (Saurida tumbil) in Retort Pouches

2021 ◽  
Author(s):  
K. Hema ◽  
P. Velayutham ◽  
C.O. Mohan ◽  
D. Sukumar ◽  
B. Sundaramoorthy ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Thermal Process ◽  
Water Immersion ◽  
Value Added ◽  
Steam Injection ◽  
Process Time ◽  
Thermally Processed ◽  
Total Process ◽  
Heat Penetration ◽  
The Difference

Background: Seafood analogue is a ready to make value added product prepared out of surimi. Thermal processing of restructured products in retort pouches such as fish ball in curry medium, surimi stew in white tripod, boneless rohu balls in curry. Also no work had done on thermal processing of shrimp analogue products in retort pouches. The main objective of this work was to develop the analogue shrimp product from lizardfish and to compare the heat penetration attributes of analogue shrimp curry and masala using retort pouches and different sterilization methods such as steam / air over pressure retort and water immersion retort.Methods: Analogue shrimp products were prepared and thermally processed in retortable pouches. About 125g of shrimp analogue product and 100g of curry (masala) were filled in retort pouches of size, 150x200mm. Air inside the pouch was exhausted by steam injection followed by heat sealing and processing at 121.1°C in a retort by steam/air over pressure retort and water immersion retort. The difference in the heat penetration characteristics of analogue shrimp products processed in retort by steam/air over pressure retort and water immersion retort were studied. Result: The results showed that minimum heating lag factor and minimum come up time led to faster heating rate which decreased total process time in imitated shrimp curry by steam/ air retort. At the same time the cook value was low in curry medium processed by steam air retort. So finally conclude that imitated shrimp curry processed by steam air retort was good.

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