The Characteristics of MOSFETs Fabricated on the Trench Sidewalls of Various Faces Using 4H-SiC (11-20) Substrates

2006 ◽  
Vol 527-529 ◽  
pp. 1297-1300
Author(s):  
Hiroyuki Fujisawa ◽  
Takashi Tsuji ◽  
Masaharu Nishiura
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Effective Channel

This paper reports the channel mobilities of MOSFETs formed on the trench sidewalls with different crystal faces including (0001), (000-1), (1-100) and (0-33-8) using 4H-SiC (11-20) substrates. Deposited poly-Si was oxidized in wet ambient to form the gate oxide, and annealed in N2O (10%) ambient. The order of drain current of trench sidewall MOSFETs was (0-33-8) > (1-100) > (000-1) = (0001). We could gain comparatively high channel mobility on the (0-33-8) face. The maximum effective channel mobility (μeff) was 35cm2/Vs, and μeff at 2.5MV/cm was 29 cm2/Vs on the (0-33-8) face.

Design and Process Issues for Silicon Carbide Power DiMOSFETS

2000 ◽  
Vol 640 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Anant K. Agarwal ◽  
Nelson S. Saks ◽  
Mrinal K. Das ◽  
Lori A. Lipkin ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Structure ◽  
Channel Mobility ◽  
Power Mosfets ◽  
Buried Channel ◽  
P Type ◽  
Very High ◽  
Effective Channel

ABSTRACTThis paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (EC) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μeff) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μeff. NO anneal, which was reported to be very effective in increasing the μeff of SiC MOSFETS in p-type epilayers, did not produce reasonable μeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μeff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.

Elevated Temperature Operation of 4H-SiC Nanoribbon Field Effect Transistors

2015 ◽  
Vol 15 (10) ◽  
pp. 7551-7554 ◽  
Author(s):  
Min Seok Kang ◽  
Susanna Yu ◽  
Sang Mo Koo
Keyword(s):  
Elevated Temperature ◽  
Plasma Etching ◽  
Field Effect ◽  
Heat Dissipation ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Top Down ◽  
Channel Mobility ◽  
Channel Thickness ◽  
Effective Channel

We fabricated 4H-SiC nanoribbon field effect transistors (FETs) of various channel thickness (tch) of 100∼500 nm by a “top–down” approach, using a lithography and plasma etching process. We studied the dependence of the device transfer characteristics on the channel geometry. This demonstrated that fabricated SiC nanoribbon FETs with a tch of 100 nm show normally-on characteristics, and have a threshold voltage of −12 V, and a maximum transconductance value of 8.8 mS, which shows improved drain current degradation of the SiC nanoribbon FETs with tch =100 nm at elevated temperature. This can be attributed to the improved heat dissipation, enhanced channel mobility, and together with widening of effective channel thickness depletion induced.

Impact of Channel Mobility Improvement Using Boron Diffusion on Different Power MOSFETs Voltage Classes

2017 ◽  
Vol 897 ◽  
pp. 537-540
Author(s):  
Victor Soler ◽  
Maria Cabello ◽  
Maxime Berthou ◽  
Josep Montserrat ◽  
José Rebollo ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Pin Diode ◽  
Boron Diffusion ◽  
Oxide Formation ◽  
Interface Quality ◽  
Channel Mobility ◽  
Power Mosfets ◽  
The Impact ◽  
Effective Channel ◽  
Drift Layer

SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO2/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

Improved Evaluation Method for Channel Mobility in SiC Trench MOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 757-760 ◽  
Author(s):  
Katsuhiro Kutsuki ◽  
Sachiko Kawaji ◽  
Yukihiko Watanabe ◽  
Shinichiro Miyahara ◽  
Jun Saito
Keyword(s):  
Evaluation Method ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Effective Field ◽  
Channel Mobility ◽  
Definition Of ◽  
Effective Channel ◽  
Dominant Influence ◽  
The Ideal

We proposed an improved method for evaluating the effective channel mobility (μeff), involving an appropriate definition of the threshold voltage (Vth) based on the ideal gate bias voltage – drain current (VG-ID) characteristics. Using this method, the dependence of μeff on the effective field (Eeff) could be evaluated even for SiC trench MOSFETs with large interface state density (Dit) values. The dominant influence on μeff in the low Eeff region was found to be Coulomb scattering caused by interface states at the SiC/SiO2 interfaces.

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

2011 ◽  
Vol 679-680 ◽  
pp. 645-648 ◽  
Author(s):  
Motoki Kobayashi ◽  
Hidetsugu Uchida ◽  
Akiyuki Minami ◽  
Toyokazu Sakata ◽  
Romain Esteve ◽  
...  
Keyword(s):  
Titanium Nitride ◽  
High Performance ◽  
Room Temperature ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Thermally Grown Oxides ◽  
Metal Gates ◽  
Blocking Voltage ◽  
Gate Oxide Integrity

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

Proton and Electron Irradiation in Oxynitrided Gate 4H-SiC MOSFET: A Recent Open Issue

2015 ◽  
Vol 821-823 ◽  
pp. 667-672 ◽  
Author(s):  
Matthieu Florentin ◽  
Mihaela Alexandru ◽  
Aurore Constant ◽  
Philippe Michel ◽  
Josep Montserrat ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Special Focus ◽  
Channel Mobility ◽  
Mos Devices ◽  
Post Annealing ◽  
Military Applications ◽  
Open Issue ◽  
Effective Channel ◽  
Open Issues

Long-term degradation of MOS devices has to be avoided in different harsh irradiated environments, especially for aerospace or military applications. In this paper, an overview of the irradiation experiments recently performed on 4H-SiC MOSFETs having an oxynitrided gate oxide is given, with a special focus on the threshold voltage and the effective channel mobility drifts. The general mechanisms taking place during irradiation and post-annealing treatments are described. Finally, new open issues recently observed by performing the temperature measurement on irradiated MOSFETs will be introduced and discussed.

scholarly journals Study and Assessment of Defect and Trap Effects on the Current Capabilities of a 4H-SiC-Based Power MOSFET

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 735
Author(s):  
Fortunato Pezzimenti ◽  
Hichem Bencherif ◽  
Giuseppe De Martino ◽  
Lakhdar Dehimi ◽  
Riccardo Carotenuto ◽  
...  
Keyword(s):  
Drain Current ◽  
Oxide Semiconductor ◽  
Temperature Dependent ◽  
Channel Mobility ◽  
Blocking Voltage ◽  
Current Voltage ◽  
Wide Range ◽  
Temperature Ranges ◽  
Joint Contribution ◽  
State Resistance

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.

scholarly journals Hot-carrier-induced degradation of drain current hysteresis and transients in thin gate oxide floating body partially depleted SOI nMOSFETs

2006 ◽  
Vol 46 (9-11) ◽  
pp. 1657-1663 ◽  
Author(s):  
J.M. Rafí ◽  
E. Simoen ◽  
K. Hayama ◽  
A. Mercha ◽  
F. Campabadal ◽  
...  
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Floating Body ◽  
Hot Carrier ◽  
Thin Gate Oxide

Analytical Treatment of Field-Effect Conduction in Polysilicon thin film Transistors

1997 ◽  
Vol 471 ◽  
Author(s):  
W. Eccleston
Keyword(s):  
Thin Film ◽  
Grain Size ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Drain Current ◽  
High Current ◽  
Analytical Treatment ◽  
Channel Mobility ◽  
Current Region ◽  
The Relationship

ABSTRACTThe drift of electrons in the channels of Thin Film Transistors is analysed for discrete grains separated by grain boundaries containing amorphous silicon. The model provides the relationship channel mobility and grain size. The relationship between drain current and the terminal voltages is also predicted. The model relates to normal high current region of transistor operation.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou
Keyword(s):  
Gate Oxide ◽  
Silicon On Insulator ◽  
Double Gate ◽  
Current Crowding ◽  
Crowding Effect ◽  
Short Channel ◽  
Channel Mobility ◽  
Channel Effect ◽  
193 Nm ◽  
Dry Etch

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.

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