Origin Analysis and Elimination of Obtuse Triangular Defects in 4° Off 4H-SiC Epitaxy

2018 ◽  
Vol 924 ◽  
pp. 168-171
Author(s):  
Kai Li Mao ◽  
Ying Min Wang ◽  
Bin Li ◽  
Gao Yang Zhao
Keyword(s):  
Growth Process ◽  
Gate Oxide ◽  
Structural Features ◽  
Confocal Microscope ◽  
Stacking Fault ◽  
Epitaxial Layers ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Origin Analysis

The obtuse triangular defects would result in higher leakage currents and the preferential gate oxide breakdown of SiC devices. The formation and structural features of obtuse triangular defects on the 4° off 4H-SiC epilayers were investigated by confocal microscope and photoluminescence image. Two structrures of obtuse triangular defects were found. By optimizing the growth process, obtuse triangular defect free epitaxial layers were abtained on SiC substrate with serveral stacking fault. The number of triangular SFs defects was less than 0.5/cm2.

Observation of Micro-Oxygen Precipitates in the Vicinity of the Oxidation-Induced Stacking Fault Ring and Their Effects on Thin Gate Oxide Breakdown

2001 ◽  
Vol 40 (Part 2, No. 12A) ◽  
pp. L1286-L1289 ◽  
Author(s):  
Hyun-Soo Kim ◽  
Ki-Sang Lee ◽  
Bo-Young Lee ◽  
Hak-Do Yoo ◽  
Seung-Ho Pyi ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Stacking Fault ◽  
Oxide Breakdown ◽  
Thin Gate Oxide ◽  
Oxygen Precipitates

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

2013 ◽  
Vol 10 (4) ◽  
pp. 150-154 ◽  
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Operation Temperature

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Correlation between Thermal Oxide Breakdown and Defects in n-Type 4H-SiC Epitaxial Wafers

2008 ◽  
Vol 600-603 ◽  
pp. 775-778 ◽  
Author(s):  
Stanislav I. Soloviev ◽  
Kevin Matocha ◽  
Greg Dunne ◽  
Zachary Stum
Keyword(s):  
Electron Beam ◽  
Epitaxial Layers ◽  
Induced Current ◽  
Leakage Currents ◽  
Oxide Breakdown ◽  
Mos Devices ◽  
Thermal Oxide ◽  
Electron Beam Induced Current

In this work, the correlation between thermal oxide breakdown and dislocations in n-type 4H-SiC epitaxial wafers has been investigated. Thermal oxide was grown by oxidation in N2O at 1250°C followed by annealing in NO atmosphere. The electron beam induced current (EBIC) technique was employed to find correlations between the electrically active defects in epitaxial layers and regions where the oxide breakdowns occurred. The test measurements of leakage currents in MOS devices were performed in order to correlate the leakage currents with number of defects in the epi-layer detected by EBIC technique.

Structural features and strength behavior of TRIP/TWIP steels

2020 ◽  
pp. 5-18
Author(s):  
D. V. Prosvirnin ◽  
◽  
M. S. Larionov ◽  
S. V. Pivovarchik ◽  
A. G. Kolmakov ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Chemical Composition ◽  
Thermomechanical Processing ◽  
Maximum Load ◽  
Structural Features ◽  
Stacking Fault ◽  
Stacking Fault Energy ◽  
Structural And Functional Properties ◽  
Twip Steels ◽  
The Creation

A review of the literature data on the structural features of TRIP / TWIP steels, their relationship with mechanical properties and the relationship of strength parameters under static and cyclic loading was carried out. It is shown that the level of mechanical properties of such steels is determined by the chemical composition and processing technology (thermal and thermomechanical processing, hot and cold pressure treatment), aimed at achieving a favorable phase composition. At the atomic level, the most important factor is stacking fault energy, the level of which will be decisive in the formation of austenite twins and / or the formation of strain martensite. By selecting the chemical composition, it is possible to set the stacking fault energy corresponding to the necessary mechanical characteristics. In the case of cyclic loads, an important role is played by the strain rate and the maximum load during testing. So at high loading rates and a load approaching the yield strength under tension, the intensity of the twinning processes and the formation of martensite increases. It is shown that one of the relevant ways to further increase of the structural and functional properties of TRIP and TWIP steels is the creation of composite materials on their basis. At present, surface modification and coating, especially by ion-vacuum methods, can be considered the most promising direction for the creation of such composites.

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Fundamental Considerations for CDM Failure in 90nm Products

2006 ◽  
Author(s):  
Nobuyuki Wakai ◽  
Yuji Kobira ◽  
Hidemitsu Egawa ◽  
Masayoshi Tsutsumi
Keyword(s):  
Breakdown Voltage ◽  
High Speed ◽  
Gate Oxide ◽  
Critical Parameters ◽  
Protection Device ◽  
Oxide Breakdown ◽  
Technology Products ◽  
Charged Device ◽  
Device Size ◽  
Fundamental Consideration

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.

scholarly journals Influence of technological factors on the characteristics of ohmic contacts of powerful AlGaN/GaN/SiC HEMT

2019 ◽  
Vol 21 (3) ◽  
pp. 182-193
Author(s):  
K. L. Enisherlova ◽  
B. K. Medvedev ◽  
E. M. Temper ◽  
V. I. Korneev
Keyword(s):  
Ohmic Contacts ◽  
Structural Features ◽  
Structural Defects ◽  
Conducting Layer ◽  
Leakage Currents ◽  
Surface Microrelief ◽  
Microwave Transistors ◽  
High Power Microwave ◽  
New Type ◽  
Power Microwave

Abstract. In this paper are considers the effect of the microrelief, dislocation structure and other defects of the epitaxial layers of the source and drain regions of the nitride HEMT transistors on the parameters of the formed ohmic contacts. The studies were carried out directly on high−power microwave transistors made of GaN/AlGaN/GaN/SiC heterostructures. Ohmic burning contacts were formed using the compositions Ti—Al—Mo—Au and Ti—Al—Ni—Au. To estimation the structural features of the contact areas, the surface microrelief at the interface of the burned contact/AlGaN and the defects formed on its surface was studied. It is shown that the resistance of the source and drain regions is largely determined by the surface microstructure at the boundary. Experimentally shown is the formation of a conducting layer in AlGaN under the ohmic contacts. The possibility of the formation of a new type of structural defects with a high aspect ratio in the contact and active areas of the devices during the formation of ohmic burned contacts is demonstrated. It is shown that the appearance of high densities of such defects leads to an increase of the device leakage currents.

Explanation of nMOSFET substrate current after hard gate oxide breakdown

2001 ◽  
Vol 59 (1-4) ◽  
pp. 155-160 ◽  
Author(s):  
B Kaczer ◽  
R Degraeve ◽  
A De Keersgieter ◽  
M Rasras ◽  
G Groeseneken
Keyword(s):  
Gate Oxide ◽  
Oxide Breakdown ◽  
Substrate Current
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