Advances in Test Wafer Reclaim Technology – Wet Stripping Porous Low-k Films with No Substrate Damage

2009 ◽  
Vol 145-146 ◽  
pp. 339-342 ◽  
Author(s):  
Mark Robson ◽  
Kristin A. Fletcher ◽  
Ping Jiang ◽  
Michael B. Korzenski ◽  
A. Upham ◽  
...  
Keyword(s):  
Film Thickness ◽  
Etch Rate ◽  
Oxide Growth ◽  
Semiconductor Processing ◽  
Related Cost ◽  
Increasing Demand ◽  
Wet Etch ◽  
Low K

In semiconductor processing, test wafers are used as particle monitors, film thickness monitors for deposition and oxide growth measurements, dry/wet etch rate monitors, CMP monitors, as well as characterizing new and existing equipment and processes. Depending on fab size and capacity, monthly test wafer usage can be tens of thousands or more. Due to the ever increasing demand for silicon between the IC and solar markets and the high cost of 300mm wafers, chip manufacturers are increasing their efforts to reduce overall spending on silicon - currently by far the largest non equipment related cost [1]. One approach taken by many chip makers is the concept of extending the usable life of test wafers by re-using them as many times as possible through a reclaim process.

High Throughput Wet Etch Solution for BEOL TiN Removal

2016 ◽  
Vol 255 ◽  
pp. 245-250
Author(s):  
Chia Jung Hsu ◽  
Chieh Ju Wang ◽  
Sheng Hung Tu ◽  
Makonnen Payne ◽  
Emanuel Cooper ◽  
...  
Keyword(s):  
Hydrogen Peroxide ◽  
High Throughput ◽  
Etch Rate ◽  
Manufacturing Processes ◽  
Mixing Ratio ◽  
Strong Base ◽  
Wet Etch ◽  
Tin Removal ◽  
Low K ◽  
Etch Residue

Sub-10 nm technology node manufacturing processes may require the use of thicker and denser TiN hard mask for patterning at the BEOL. The modified TiN, which tends to be more chemically robust, must be removed using a wet etch process, while maintaining typical throughput - no extension of typical wet etch process times. To satisfy these needs, a new TiN etching accelerator was found that enhanced the activity of peroxide-related species in a wet etch chemical formulation that achieved increased TiN etch rate relative to formulation without TiN etch rate accelerator (Sample 1), while also minimizing the damage to ultra-low-k inter layer dielectric (ILD) layer by a strong base, also present in the formulation. We report here the result of a solvent based formulation, which adopted the TiN etching accelerator. The formulation was able to maintain TiN etch rate and remove post-etch residue, while remaining selective to ultra-low-k ILD, Co and Cu. The TiN etch rate of the accelerator enhanced formulation can be further tuned by modifying the process temperature or the hydrogen peroxide to formulation mixing ratio and has the potential capability to process > 400 wafers.

Feasibility to Fabricate the 45° Slant with Anisotropic Silicon Etching in NaOH Solution

2012 ◽  
Vol 503-504 ◽  
pp. 615-619 ◽  
Author(s):  
Alonggot Limcharoen ◽  
Chupong Pakpum ◽  
Pichet Limsuwan
Keyword(s):  
Data Storage ◽  
Etch Rate ◽  
Silicon Etching ◽  
Naoh Solution ◽  
Conventional Photolithography ◽  
Sio2 Mask ◽  
P Type ◽  
Anisotropic Silicon Etching ◽  
Wet Etch ◽  
Laser Light Source

The experiments to study the feasibility to fabricate the 45 slant on p-type (100)-oriented silicon wafer were done. The various mask shapes, rectangular, cross, circle and boomerang, were patterned on the SiO2 mask by utilizing the conventional photolithography and dry etching process for investigating the anisotropic wet etch characteristic. The edge of masks were align in two crystal direction, 110 and 100 that is allowable to get a better understanding about the crystal orientation and the angle between planes in a crystal system. The very low etch rate,  50 nm/min, process regime was selected to fabricate the 45 slant with the concept is the lowest of an overall etch rate in the system to reach the level that is possible to detect the (110) plane. The etch recipe can be used for the next development work to built a housing of the laser light source for applying in a data storage technology.

Comparison of the Fracture Behavior of Brittle ILD Films used in the BEOL in Dry and Wet Environment using Nanoindentation

2006 ◽  
Vol 914 ◽  
Author(s):  
Eva Simonyi ◽  
Michael Lane ◽  
Erik Liniger ◽  
Alfred Grill
Keyword(s):  
Fracture Toughness ◽  
Film Thickness ◽  
Manufacturing Process ◽  
Fracture Behavior ◽  
Imaging Methods ◽  
Afm Imaging ◽  
Critical Film Thickness ◽  
Low K

AbstractDuring the manufacturing process of the BEOL the low-k brittle ILD dielectrics are exposed to wet environments. These environments could and do affect the films fracture toughness, the so called critical film thickness, above which spontaneous cracking occurs. Nanoindentation combined with AFM imaging methods allow to study these phenomena.

Low k Film Etch in Applied Materials eMxP+ Chamber

1998 ◽  
Vol 544 ◽  
Author(s):  
Melissa Yu ◽  
Hongching Shan ◽  
Ashley Taylor
Keyword(s):  
Dielectric Constant ◽  
Etch Rate ◽  
Process Conditions ◽  
Plasma Etch ◽  
Absolute Value ◽  
Lower Dielectric Constant ◽  
Profile Control ◽  
Etch Stop ◽  
Anisotropic Etch ◽  
Low K

ABSTRACTThe materials with lower dielectric constant ( low k ) have been attracting attention recently because the low k material has the potential to be used in place of SiO2 in ULSI. In this work, we focused on evaluating organic low k material performance with plasma etch in the Applied Material's eMxP+ anisotropic etch chamber. The films studied were Dow Chemical BCB and Silk, Allied Signal Flare 2.0, and Du Pont FPI. The feature sizes of the wafer s were 0.25 to 1 micron trenches. Du Pont FPI resulted in the highest achieved etch rate of more than lum/min, followed by BCB, and Flare. The microloading study indicated that the etch rate microloading is less than 10% between lum and 0.25 urn feature sizes, which suggests that the chance of etch stop for a high aspect ratio features will be small. The profile could vary from bowing to vertical, to tapering by using different process conditions, mainly by temperature. The FP1 profile was more tapered than those of BCB and Flare when the same process was used to etch the same type of patterned wafer having these three different low k films. The detailed study showed that the trend of etch rate and profile for BCB and Flare film etch were similar, but that the absolute value for profile, as well as the trend of etch rate uniformity and profile were somewhat different. In conclusion, low k materials can be etched in AMAT traditional dielectric chamber (eMxP+) with a good etch rate and profile control.

Morphological and Structural Evolution of an Ultra-low-k Dielectric During the Porogen Removal

2006 ◽  
Vol 914 ◽  
Author(s):  
Diane Rebiscoul ◽  
Héléne Trouvé ◽  
Bruno Remiat ◽  
Laurence Clerc ◽  
Didier Louis ◽  
...  
Keyword(s):  
Refractive Index ◽  
Etch Rate ◽  
Structural Evolution ◽  
Integration Scheme ◽  
Thermal Cure ◽  
Crosslinking Degree ◽  
Cure Temperature ◽  
The Impact ◽  
Low K ◽  
Complex Gradient

AbstractThe use of porous ultra-low-k materials between interconnections for sub 45nm technologies has introduced some barrier diffusion and mechanical problems. In order to avoid the problems caused by the porosity, a hybrid dense material (porogen and matrix) can be used in an alternate integration scheme. In this approach, the porogen is removed after CMP steps by a thermal cure or UV assisted thermal cure. In this work, we have first characterized the impact of the temperature and the duration of the thermal cure on the material. The crosslinking degree increases and the porogen amount decreases with increasing cure temperature. The most important impact of the curing duration happens between 350°C and 400°C. The increase of the curing duration leads to an increase of the porogen loss and a decrease of the refractive index. Secondly, in order to assess the structure of the layer as a function of the depth, the material was etched in a 0.05% HF solution and then characterized. According to the temperature and duration of the cure, the etch-rate can vary as a function of the material depth. This variation is related to a complex gradient inside the material.

Study of Porous Organic Ultra Low K Materials After Treatment With Various Etching and Cleaning Plasma

2004 ◽  
Author(s):  
Dong Lu ◽  
Vanissa Lim ◽  
B. Ramana Murthy ◽  
Rakesh Kumar ◽  
Du An Yan ◽  
...  
Keyword(s):  
Film Thickness ◽  
Critical Role ◽  
Interface Roughness ◽  
Surface Roughening ◽  
Structure And Property ◽  
Atomic Force ◽  
Plasma Treatments ◽  
Silk Films ◽  
Process Compatibility ◽  
Low K

Abstract In the selection of ultra low k materials, process compatibility is a very important factor. Plasma processing plays a critical role in enhanced interconnect integration. It is therefore important to study plasma interaction with the ultra low k materials and its effects on the structure and property of these materials. X-ray reflectivity (XRR) measurement can be used to measure film thickness, density and interface roughness, which are important parameters to check for after plasma treatments. In the current study, porous SiLK (p-SiLK) was treated with various plasmas, such as O2, O2/N2, H2/N2, CH2F2/Ar and CF4/O2. XRR results indicate that the density of the p-SiLK films remains unchanged after various plasma treatments. Surface roughening occurs during the plasma treatments, accompanied by the decrease in film thickness. Plasma-induced surface roughening was also observed using atomic force microscope (AFM). Such roughening is more severe for plasma treatments using oxygen-containing plasmas. FTIR analysis indicates that the chemical structure of the p-SiLK films is not significantly affected by plasma treatment. It is reasonable to conclude that oxidation of the surface plays a major role in the plasma-induced change in surface roughness and film thickness.

Silicon Wafer Thinning to Reveal Cu TSV

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001673-001700 ◽  
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Ramey Youssef
Keyword(s):  
Silicon Wafer ◽  
Etch Rate ◽  
Cost Effective ◽  
Silicon Etching ◽  
3D Integration ◽  
Process Flow ◽  
Cost Effective Method ◽  
Etch Rates ◽  
Wet Etch ◽  
Wafer Thinning

3D Integration is becoming a reality in device manufacturing. The TSV Middle process is becoming the dominant integration scenario. For this process flow the silicon wafer needs to be thinned to reveal the Cu TSV. Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes CMP and plasma have been used to complete the final thinning of the silicon. This paper will describe a simple, cost effective method to wet etch the remaining silicon to reveal the Cu TSVs. KOH is selected as the etchant since it will not attack the TSV materials and has a higher etch rate than TMAH. The development of processes with optimum etch rates and uniformity for silicon etching along with no attack of the Cu via or oxide liner and effective post cleaning to remove residual Potassium will be presented.

Porous Low-k Wet Etch in HF-Based Solutions: Focus on Cleaning Process Window, "Pore-Sealing" and "k Recovery"

2009 ◽  
Vol 145-146 ◽  
pp. 295-302 ◽  
Author(s):  
Lucile Broussous ◽  
W. Puyrenier ◽  
D. Rebiscoul ◽  
V. Rouessac ◽  
A. Ayral
Keyword(s):  
Surface Layer ◽  
Process Window ◽  
Cleaning Process ◽  
Design Rules ◽  
Porosity Evolution ◽  
Pore Sealing ◽  
Modified Surface ◽  
Wet Etch ◽  
Low K ◽  
Modified Surface Layer

In this study, the compatibility of "HF-Based" cleaning with porous low-k integration, and “pore-sealing” approach was investigated, and specific attention was paid to ultra low-k porosity evolution. We also tried to demonstrate if "k-recovery" could be achieved by thinning the modified surface layer in the pattern trench walls (plasma damaged layer), for 65nm and 45 nm design rules.

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