Feasibility to Fabricate the 45° Slant with Anisotropic Silicon Etching in NaOH Solution

2012 ◽  
Vol 503-504 ◽  
pp. 615-619 ◽  
Author(s):  
Alonggot Limcharoen ◽  
Chupong Pakpum ◽  
Pichet Limsuwan
Keyword(s):  
Data Storage ◽  
Etch Rate ◽  
Silicon Etching ◽  
Naoh Solution ◽  
Conventional Photolithography ◽  
Sio2 Mask ◽  
P Type ◽  
Anisotropic Silicon Etching ◽  
Wet Etch ◽  
Laser Light Source

The experiments to study the feasibility to fabricate the 45 slant on p-type (100)-oriented silicon wafer were done. The various mask shapes, rectangular, cross, circle and boomerang, were patterned on the SiO2 mask by utilizing the conventional photolithography and dry etching process for investigating the anisotropic wet etch characteristic. The edge of masks were align in two crystal direction, 110 and 100 that is allowable to get a better understanding about the crystal orientation and the angle between planes in a crystal system. The very low etch rate,  50 nm/min, process regime was selected to fabricate the 45 slant with the concept is the lowest of an overall etch rate in the system to reach the level that is possible to detect the (110) plane. The etch recipe can be used for the next development work to built a housing of the laser light source for applying in a data storage technology.

Silicon Wafer Thinning to Reveal Cu TSV

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001673-001700 ◽  
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Ramey Youssef
Keyword(s):  
Silicon Wafer ◽  
Etch Rate ◽  
Cost Effective ◽  
Silicon Etching ◽  
3D Integration ◽  
Process Flow ◽  
Cost Effective Method ◽  
Etch Rates ◽  
Wet Etch ◽  
Wafer Thinning

3D Integration is becoming a reality in device manufacturing. The TSV Middle process is becoming the dominant integration scenario. For this process flow the silicon wafer needs to be thinned to reveal the Cu TSV. Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes CMP and plasma have been used to complete the final thinning of the silicon. This paper will describe a simple, cost effective method to wet etch the remaining silicon to reveal the Cu TSVs. KOH is selected as the etchant since it will not attack the TSV materials and has a higher etch rate than TMAH. The development of processes with optimum etch rates and uniformity for silicon etching along with no attack of the Cu via or oxide liner and effective post cleaning to remove residual Potassium will be presented.

Single-Crystal Silicon Etching Characteristics Using Excimer Laser Cℓ2 GAS

1983 ◽  
Vol 29 ◽  
Author(s):  
T. Arikado ◽  
M. Sekine ◽  
H. Okano ◽  
Y. Horiike
Keyword(s):  
Single Crystal ◽  
Gas Phase ◽  
Excimer Laser ◽  
Plasma Etching ◽  
Etch Rate ◽  
Single Crystal Silicon ◽  
Silicon Etching ◽  
Crystal Silicon ◽  
Direct Irradiation ◽  
P Type

ABSTRACTSingle-crystal Si etching characteristics using an excimer laser (308 nm, XeCℓ) in the Cℓ2 gas have been studied. In lightly doped n-type and p-type Si, the etch rate of (100) is higher than that of (111), thus the (111) sidewall appears clearly for the irradiation to (100), while both orientations show almost the same etch rates in n+-doped Si. The n-type Si is etched spontaneously even by photo-dissociated Cℓ radicals generated in the gas phase, but no p-type Si etching occurs without direct irradiation. In addition, both types of etch rate-dependence on sheet resistance demonstrate that the number of electrons in the conduction band plays an essential role in the Si etching. This fact supports the field-assisted mechanism in the plasma etching proposed by Winters.

Investigation of Choline Hydroxide for Selective Silicon Etch from a Gate Oxide Failure Analysis Standpoint

2002 ◽  
Author(s):  
Valentina Korchnoy
Keyword(s):  
Aqueous Solution ◽  
Oxide Film ◽  
Failure Analysis ◽  
Surface Quality ◽  
Etch Rate ◽  
Gate Oxide ◽  
Silicon Etching ◽  
Poly Silicon ◽  
Wet Etch

Abstract A robust procedure for poly-silicon wet etch selective to SiO2 is presented. The procedure is applicable for CMOS devices and maintains the integrity of the gate oxide film. The technique uses a 50% wt. choline hydroxide aqueous solution. The optimum etching conditions, which allow exposure of gate oxide to enable its further inspection using SEM or AFM were determined. An investigation of general silicon etching characteristics of choline hydroxide, as etch rate, selectivity and surface quality, has been carried out as well.

Silicon Etching Mechanisms - Doping Effect

1984 ◽  
Vol 38 ◽  
Author(s):  
Young H. Lee ◽  
Mao-Min Chen ◽  
A. A. Bright
Keyword(s):  
Plasma Etching ◽  
Etch Rate ◽  
Opposite Polarity ◽  
Doping Effect ◽  
Inductive Heating ◽  
Silicon Etching ◽  
Polysilicon Film ◽  
Reactive Plasma ◽  
Heavily Doped ◽  
P Type

AbstractEtch rates of heavily doped silicon films (n- and p-type) and undoped polysilicon film were studied during plasma etching and also during reactive ion etching in a CF4/O2 plasma. The etch rate of undoped Si was lower than the n+ Si etch rate, but higher than the p+ Si etch rate, when the RF inductive heating by the eddy current was minimized by using thermal backing to the water-cooled electrode. The thermal activation energy for spontaneous chemical etching was measured to be 0.10 eV, independent of the doping characteristics. This doping effect may be explained by the opposite polarity of the space charge present in the depletion layer of n+ Si and p+ Si during reactive plasma etching.

Wet Etch Rate Behavior of Poly-Si in TMAH Solution at Various Ambient Gas Conditions

2014 ◽  
Vol 219 ◽  
pp. 78-80
Author(s):  
Euing Lin ◽  
Ted Guo ◽  
C.C. Chien ◽  
M.H. Chang ◽  
Wesley Yu ◽  
...  
Keyword(s):  
Etch Rate ◽  
Depletion Region ◽  
Electrical Performance ◽  
Bulk Silicon ◽  
Gate Structure ◽  
Cavity Structure ◽  
Rate Behavior ◽  
Ambient Gas ◽  
P Type ◽  
Wet Etch

As the demand for greater speed in semiconductor devices continues, a typical method of increasing charge mobility is to maximise the silicon strain at the depletion region in p-type transistors through the implementation of “Sigma Cavity” structures in the bulk silicon on either side of the gate structure. These structures, when filled, exhibit a uniaxial strain in the depletion region thus, increasing the charge transport speed [1]. The shape of the Sigma Cavity structure is important in maximising the strain in this region, thus strict control of the shape dimensions is imperative to the electrical performance of the device.

scholarly journals Optimization of deep silicon etching process for microstructures fabrication

2021 ◽  
Vol 2086 (1) ◽  
pp. 012190
Author(s):  
V Kuzmenko ◽  
A Miakonkikh ◽  
K Rudenko
Keyword(s):  
Bias Voltage ◽  
Etch Rate ◽  
Etching Process ◽  
Cyclic Process ◽  
Wall Roughness ◽  
Silicon Etching ◽  
Etching Depth ◽  
Deep Etching ◽  
Anisotropic Silicon Etching

Abstract The paper presents the study of cyclic process of deep anisotropic silicon etching, called Oxi-Etch, in which the steps of etching and oxidation alternate, allowing deep etching of silicon with an anisotropic profile. This process forms typical for cyclic etching process sidewall profile called scalloping. Opportunities for modification and optimization of the process for specific application were investigated. The effects of optimization of the bias voltage and the duration of the etching step on the parameters of the resulting structures, such as the etching depth, wall roughness, and the accuracy of transferring the lithographic size, are considered. Balance between etch rate and scalloping was established.

Wet Etching Technique to Reduce Pyramidal Hillocks for Anisotropic Silicon Etching in NaOH/IPA Solution

2015 ◽  
Vol 659 ◽  
pp. 681-685
Author(s):  
Chu Pong Pakpum
Keyword(s):  
Etch Rate ◽  
Wet Etching ◽  
High Yield ◽  
Solution Temperature ◽  
Silicon Etching ◽  
Etching Technique ◽  
Ultrasonic Agitation ◽  
The Difference ◽  
Etched Surface ◽  
Anisotropic Silicon Etching

The various methods of silicon wet etching techniques, which utilize ultrasonic agitation to reduce pyramidal hillocks in etched patterns, were evaluated in NaOH+IPA solution. The comparison of the etching methods composed of; 1.) no agitation + sample horizontally orientated, 2.) ultrasonic agitation + sample horizontally orientated, 3.) ultrasonic agitation + sample vertically orientated, and 4.) ultrasonic with rotation agitation + sample vertically orientated. It was found that the percentages of the etched patterns presenting hillocks after etching were 100%, 79.77%, 32.67% and 2.62%, respectively. Ultrasonic coupled with rotation agitation along with the sample vertically orientated is the most powerful etching technique, offering a high yield of smooth etched surface. The difference in etch rate between without agitation and applying ultrasonic agitation was not observed in this experiment, as it was operated in a solution temperature 60-65°C and a 275nm/min etch rate was achieved. The theories that relate to each evaluated method are also discussed.

ИССЛЕДОВАНИЕ ПРОЦЕССА ГЛУБОКОГО ТРАВЛЕНИЯ КРЕМНИЯ С МИНИМАЛЬНОЙ ШЕРОХОВАТОСТЬЮ СТЕНОК И ДНА СТРУКТУР

2020 ◽  
Vol 96 (3s) ◽  
pp. 668-675
Author(s):  
Я.А. Мирошкин
Keyword(s):  
Analytical Model ◽  
Phenomenological Description ◽  
Silicon Etching ◽  
Anisotropic Silicon Etching

Данная работа посвящена исследованию процессов глубокого анизотропного травления кремния. В качестве предложенных методов были проанализированы два подхода - Bosch и Cryo. Представлено феноменологическое описание вышеупомянутых методов, проведен анализ эксперимента по криогенному травлению кремния, полученный на базе ФТИАН, также предложена аналитическая модель Cryo-процесса. This work is devoted to the study of the processes of deep anisotropic silicon etching. Two approaches (Bosch and Cryo) have been analyzed as proposed methods. The phenomenological description of the above mentioned methods has been presented, the analysis of the experiment on cryogenic etching of silicon obtained on the basis of FTIAN has been carried out, as well as an analytical model of Cryo process has been proposed.

Advances in Test Wafer Reclaim Technology – Wet Stripping Porous Low-k Films with No Substrate Damage

2009 ◽  
Vol 145-146 ◽  
pp. 339-342 ◽  
Author(s):  
Mark Robson ◽  
Kristin A. Fletcher ◽  
Ping Jiang ◽  
Michael B. Korzenski ◽  
A. Upham ◽  
...  
Keyword(s):  
Film Thickness ◽  
Etch Rate ◽  
Oxide Growth ◽  
Semiconductor Processing ◽  
Related Cost ◽  
Increasing Demand ◽  
Wet Etch ◽  
Low K

In semiconductor processing, test wafers are used as particle monitors, film thickness monitors for deposition and oxide growth measurements, dry/wet etch rate monitors, CMP monitors, as well as characterizing new and existing equipment and processes. Depending on fab size and capacity, monthly test wafer usage can be tens of thousands or more. Due to the ever increasing demand for silicon between the IC and solar markets and the high cost of 300mm wafers, chip manufacturers are increasing their efforts to reduce overall spending on silicon - currently by far the largest non equipment related cost [1]. One approach taken by many chip makers is the concept of extending the usable life of test wafers by re-using them as many times as possible through a reclaim process.

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