A Systematic Approach to Thinning Silicon Wafers to the sub-40μm Thickness Range

2006 ◽  
Vol 3 (2) ◽  
pp. 86-94 ◽  
Author(s):  
Parthiban Arunasalam ◽  
Matthew H. Gordon ◽  
Leonard W. Schaper
Keyword(s):  
Systematic Approach ◽  
Silicon Wafers ◽  
Mechanical Polishing ◽  
Thickness Variation ◽  
Wafer Thickness ◽  
Chemical Etch ◽  
Custom Made ◽  
Carrier Wafer ◽  
Total Thickness Variation ◽  
Wafer Thinning

The present trend in electronics packaging is the stacking of die at the wafer or chip level. However to ensure stacked chip packages maintain overall low height and weight package profile, silicon wafers have to undergo extensive wafer thinning processes. In this work, a systematic approach to thinning silicon wafers down to sub-40μm in thickness is presented. This paper will cover a detailed three stage wafer thinning method, which includes the mechanical back-lapping method for the bulk removal process and a combination of mechanical polishing and spin-spray wet chemical etch method for the fine removal wafer thinning process. The results will show that by just utilizing the mechanical back-lapping and mechanical polishing process the wafers can be easily thinned from 380μm to less than 50μm with ±2.5μm Total Thickness Variation (TTV). These back-lapped wafers are then further thinned by the spin-spray etching method to achieve final wafer thickness of less than 40μm. The paper will also show that by utilizing a modified carrier wafer, the handling of these sub-40μm ultra-thin wafers do not require custom made tools and can be easily integrated into existing wafer handling tools.

Manufacturable 300mm Wafer Thinning for 3D Interconnect Applications

2010 ◽  
Vol 1249 ◽  
Author(s):  
Jamal Qureshi ◽  
Raymond Caramto ◽  
Stephen Olson ◽  
Jerry Mase ◽  
Toshihiro Ito ◽  
...  
Keyword(s):  
Thickness Variation ◽  
Force Microscopy ◽  
Critical Elements ◽  
Atomic Force ◽  
Transmission Electron ◽  
Wafer Thickness ◽  
Total Thickness Variation ◽  
Silicon Vias ◽  
Wafer Thinning ◽  
Thinning Process

Abstract3D interconnect wafer-to-wafer or die-to-wafer integration requires a wafer thinning operation to expose copper (Cu)-filled through-silicon vias (TSVs) from the backside of the wafer. The wafer thinning flow uses edge trim, backgrind, backpolish, and chemical mechanical polishing (CMP). This paper presents an overview of the wafer grinding process. We have demonstrated the capability to edge-trim and backgrind 300 mm TSV and non-TSV wafers down to 30 microns (μm) while bonded to a handle wafer. TSV wafers were further processed on a CMP tool to remove the last few microns of Si, exposing the Cu-filled TSVs. Metrology techniques were used to inspect and measure the wafer edge trim and final thinned wafer thickness. The quality of the thinned wafer was characterized by atomic force microscopy (AFM) to observe surface roughness and by transmission electron microscopy (TEM) to quantify crystalline damage below the surface of the thinned wafer. Further characterization included measuring wafer thickness, total thickness variation (TTV), bow, and warp. Exposed TSVs were characterized by laser microscope to measure the height of Cu protrusions. These critical elements of a manufacturing-worthy 300 mm wafer thinning process for 3D are discussed.

Production Proven, High Precision Temporary Bond/De-bond Process

2013 ◽  
Vol 2013 (1) ◽  
pp. 000861-000865 ◽  
Author(s):  
Blake Dronen ◽  
Aric Shorey ◽  
B.K. Wang ◽  
Leon Tsai
Keyword(s):  
High Precision ◽  
Support System ◽  
Thickness Variation ◽  
Total Thickness ◽  
Critical Step ◽  
Low Coherence ◽  
Total Thickness Variation ◽  
Thinning Operations ◽  
Wafer Thinning

Wafer thinning represents a critical step in 2.5D and 3D-IC integration. Achieving low total thickness variation (TTV) of a bonded stack is essential since it directly impacts the TTV of the thinned device wafer. It is essential to understand and utilize appropriate processes and materials that provide precision bonded stacks prior to thinning operations in order to achieve high process yields. The 3M™ Wafer Support System and Corning's precision glass carrier wafers were used to produce bonded stacks. Leveraging metrology tools like the Flatmaster MSP-300 and low coherence interferometric probes allow for characterization of the TTV of each layer of a bonded stack and better understanding of the stack-up as well as how to minimize stack TTV. The ability to deliver stack TTV of < 2 um in a repeatable manner has been demonstrated.

Development of Ultra-Precision Grinder for 300mm Wafers

2012 ◽  
Vol 565 ◽  
pp. 609-614 ◽  
Author(s):  
X.L. Zhu ◽  
Z.G. Dong ◽  
Ren Ke Kang ◽  
D.M. Guo
Keyword(s):  
Shape Control ◽  
State Of The Art ◽  
Surface Shape ◽  
Wafer Surface ◽  
Thickness Variation ◽  
Grinding Forces ◽  
Wafer Thickness ◽  
Ultra Precision ◽  
Total Thickness Variation ◽  
And Control

This study presents design of an ultra-precision wafer grinder which incorporates state-of-the-art automatic supervision and control system. The wafer grinder is characterized by wafer surface shape control, grinding forces and wafer thickness monitoring systems. The design provides a totally integrated solution to the ultra-precision grinder that is capable of grinding silicon wafers with surface roughness Ra<3 nm and total thickness variation<2µm/300mm.

scholarly journals The effect of the chuck shape on the wafer topography in back grinding of wafer with outer rim

2021 ◽  
Vol 13 (10) ◽  
pp. 168781402110504
Author(s):  
Xianglong Zhu ◽  
Weihua Yao ◽  
Xiaoguang Guo ◽  
Renke Kang ◽  
Muhammad Jawad Ahmad
Keyword(s):  
Integrated Circuits ◽  
Great Influence ◽  
Silicon Wafers ◽  
Thickness Variation ◽  
Grinding Wheel ◽  
Inclination Angles ◽  
Radial Thickness ◽  
Total Thickness Variation ◽  
Novel Method ◽  
The Mathematical Model

Back Grinding of Wafer with Outer Rim (BGWOR) is a novel method for carrier-less thinning of silicon wafers. Silicon wafers are widely used in integrated circuits (ICs). The topography of the wafer will not only directly affect the efficiency of subsequent processing of semiconductor devices, but correspondingly affect the performance and life of these devices. However, there are few studies on the shape of the ground wafer in BGWOR. In this paper, the mathematical model of the wafer topography in BGWOR was developed. With this model, the radial thickness and total thickness variation (TTV) of a wafer under different parameters, including inclination angles and radii of grinding wheel for dressing chuck, were simulated by MATLAB. Inclination angles and radii of grinding wheels for the dressing chuck had a great influence on the radial thickness and TTV of a wafer in the BGWOR. Lastly, the pilot experiments were conducted to validate the theoretical model of grinding topography and TTV of the wafer in BGWOR. To enhance the flatness of the ground wafer, it is essential to control the shape of the dressing chuck. The research results are helpful to the optimization of the dressing process of the chuck in the BGWOR.

Laser Ultrasonic Instrumentation for Accurate Temperature Measurement of Silicon Wafers in Rapid Thermal Processing Systems

1998 ◽  
Vol 525 ◽  
Author(s):  
Dan Klimek ◽  
Brian Anthonyt ◽  
Agostino Abbate ◽  
Petros Kotidis
Keyword(s):  
Temperature Measurement ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Silicon Wafers ◽  
Thickness Variation ◽  
Laser Ultrasonic ◽  
Ultrasonic Methods ◽  
Wafer Thickness ◽  
Accurate Temperature ◽  
Accurate Temperature Measurement

ABSTRACTResults are presented that demonstrate the use of laser ultrasonic methods to determine the temperature of silicon wafers under conditions consistent with applications in the RTP industry. The results show that it is possible to measure the temperature of Si(100) wafers to an accuracy approaching ± 1°C (1σ) even with wafer thickness variation over a range of 2 to 3 percent.

Precision Grinding of Ultra-Thin Quartz Wafers

1993 ◽  
Vol 115 (3) ◽  
pp. 258-262 ◽  
Author(s):  
T. G. Bifano ◽  
J. B. Hosler
Keyword(s):  
Resonant Frequency ◽  
Bulk Acoustic Wave ◽  
Thickness Variation ◽  
Precision Grinding ◽  
Wafer Thickness ◽  
Total Thickness Variation ◽  
Crystal Oscillators ◽  
Quartz Wafer ◽  
A New Technique ◽  
Structural Loop

For bulk acoustic wave quartz resonators, the central resonant frequency is inversely proportional to the wafer thickness. The tolerance of the resonant frequency is directly proportional to the total thickness variation of the quartz wafer. To increase the operating frequency while preserving a high tolerance on frequency, thinner quartz wafers with better thickness tolerances are needed. This paper describes the design and implementation of a precision grinding apparatus capable of producing ultra-thin quartz wafers to better thickness tolerances than previously achieved. A distributed-stress fixturing method that permits machining of ultra-thin, brittle substrates is described. The machine’s precision has been achieved through a high stiffness structural loop and real-time position feedback control. Optical interferometry is used in a new technique to measure thickness variation over the entire wafer. This research will enable production of quartz crystal oscillators with higher frequencies and better quality for the resonator industry.

scholarly journals A Study of the Effect of Back Grind Wheels on Wafer Edge Chippings and Die Strength

2020 ◽  
pp. 8-14
Author(s):  
Bryan Christian S. Bacquian
Keyword(s):  
Mobile Phones ◽  
Integrated Circuit ◽  
Thickness Variation ◽  
Total Thickness ◽  
Grinding Wheels ◽  
Abrasive Material ◽  
Total Thickness Variation ◽  
Output Characteristics ◽  
Wafer Thinning ◽  
Wafer Edge

The drive for thinner package architecture is already becoming a necessity. There were a need of thinner Integrated Circuit or IC in order to fit in to thinner applications like mobile phones. One of the major semiconductor process that enables miniaturization was wafer back grinding. The process involves wafer thinning to a required thickness with the use of back grinding wheels that serve as the abrasive material. The paper will discuss the effect of back grind input parameters like step grinding and wheel grit size to its output characteristics like total thickness variation, edge chippings and die strength. Total thickness variation will define if the new wheel will not affect the variation with the wafer. On the other hand, edge chippings and die strength will define the reliability of the die on different conditions of the package. Lastly, these 3 characteristics will establish the manufacturability of the process as it will eliminate the probability of wafer breakage.

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