High-speed SnAG Solder Electroplating Process and Developments on Cost Reduction

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000717-000753
Author(s):  
Bob Forman
Keyword(s):  
High Speed ◽  
Consumer Electronics ◽  
Wafer Level ◽  
Solder Bumps ◽  
New Process ◽  
Snag Solder ◽  
Single Use ◽  
Current Densities ◽  
Electroplating Process ◽  
Short Time

The use of wafer level packaged ICs with Lead (Pb) free Tin Silver (SnAg) solder bumps is prevalent in consumer electronics. One method of making these bumps is by electroplating. The current process requires the use of a complex and expensive, single use chemistry. These chemistries do provide smooth, void free bumps, but with a very high Cost of Ownership (COO). Up to now these chemistries were expensive to operate, mainly because they are used for a short time and then disposed. This paper will discuss a new process using chemistry that provides improved COO by incorporating higher plating rates with recycling of used chemistry. With this process it is possible to recover nearly 100% of the metals, acids and organic agents previously discharged as waste. The recovered chemistry is then processed and certified to be reused in the originating fab, resulting in virtually zero waste. In addition to closed loop recycling, the process also forms bumps at a higher rate, by plating at higher current densities, with no trade-off in bump performance.

Sub-100 μm SnAg Solder Bumping Technology and the Bump Reliability

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Xiaoqin Lin ◽  
Le Luo
Keyword(s):  
Cu6sn5 Phase ◽  
X Ray ◽  
Solder Bumps ◽  
Average Shear Strength ◽  
Average Shear ◽  
Snag Solder ◽  
Packaging Industry ◽  
Negative Impacts ◽  
Free Solder ◽  
Electroplating Process

Lead-free solder bumping and its related interconnection and reliability are becoming one of the important issues in today’s electronic packaging industry. In this paper, alloy electroplating was used as SnAg solder bumping process. Multiple reflow was preformed on as-plated solder bumps. Scanning electron microscopy and energy dispersive X-ray analysis were used to investigate the intermetallic compound and microvoids of cross-sectioned solder bump. Shear test was used to evaluate the reliabilities of the SnAg bumps. The 13×13 area-array Sn/3.0Ag solder bumps of 70 μm in height and 90 μm in diameter were fabricated with a smooth and shiny surface and with a uniform distribution of Ag. During multireflow, the scalloped Cu6Sn5 phase grows by a ripening process. Volume shrinkage was the main reason for the formation of microvoids during multireflow. The average shear strength of solder bumps on TiW/Cu under bump metallurgy (UBM) increased with reflow times. The electroplating process is suitable for mass production of well-controlled geometry and uniformity of SnAg solder bumps. Microvoids have trivial negative impacts on the solder bonds. The combination of TiW/Cu UBM and SnAg solder is reliable.

scholarly journals Estimation of Current Density Using High-Speed-Camera Recordings in a Model Spark Gap during Surge Currents

2019 ◽  
Vol 6 (1) ◽  
pp. 60-64
Author(s):  
T. H. Kopp ◽  
E. Peters ◽  
M. Kurrat
Keyword(s):  
Current Density ◽  
Radiation Intensity ◽  
High Speed ◽  
Experimental Investigations ◽  
High Speed Camera ◽  
Spark Gap ◽  
Plasma State ◽  
Development Processes ◽  
Current Densities ◽  
Short Time

<p>For experimental investigations of short time plasma in spark gaps, as used in surge protective devices, high-speed camera recordings are used frequently. The analysis of these recordings provides further details regarding the plasma state and distribution. These deduced details are used to assist research and development processes. <br />To increase the benefit of high-speed camera recordings an empirical model is presented to improve the picture analysis. In this model the recorded radiation intensity is empirically related to the current density within a spark gap. Therefore a specially adapted model spark gap was developed and tested. In this model spark gap areas with homogenous current densities occur. These current densities are determined in the experimental setup through current measurements with separated electrodes. Additionally, the relative radiation intensity between the electrodes is identified using high-speed camera recordings. An empirical correlation between these two measurement values was found and is discussed. <br />It confirmed that the determined correlation improve the mostly intuitive interpretation of high speed camera recordings in spark gaps.</p>

scholarly journals Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies

MRS Advances ◽  
2020 ◽  
Vol 5 (37-38) ◽  
pp. 1929-1935
Author(s):  
Kimberly Beers ◽  
Andrew E. Hollowell ◽  
G. Bahar Basim
Keyword(s):  
Flip Chip ◽  
Processing Parameters ◽  
Wafer Surface ◽  
Bump Height ◽  
Treatment Techniques ◽  
Solder Bumps ◽  
3D Packaging ◽  
Snag Solder ◽  
Current Densities ◽  
Silicon Vias

AbstractCopper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.

scholarly journals Neuro-Inspired Computing with Spin-VCSELs

2021 ◽  
Vol 11 (9) ◽  
pp. 4232
Author(s):  
Krishan Harkhoe ◽  
Guy Verschaffelt ◽  
Guy Van der Sande
Keyword(s):  
Processing Speed ◽  
Delay Time ◽  
High Speed ◽  
State Of The Art ◽  
Polarization Modulation ◽  
Time Interval ◽  
Computing Technique ◽  
High Modulation ◽  
Short Time ◽  
Modulation Speed

Delay-based reservoir computing (RC), a neuromorphic computing technique, has gathered lots of interest, as it promises compact and high-speed RC implementations. To further boost the computing speeds, we introduce and study an RC setup based on spin-VCSELs, thereby exploiting the high polarization modulation speed inherent to these lasers. Based on numerical simulations, we benchmarked this setup against state-of-the-art delay-based RC systems and its parameter space was analyzed for optimal performance. The high modulation speed enabled us to have more virtual nodes in a shorter time interval. However, we found that at these short time scales, the delay time and feedback rate heavily influence the nonlinear dynamics. Therefore, and contrary to other laser-based RC systems, the delay time has to be optimized in order to obtain good RC performances. We achieved state-of-the-art performances on a benchmark timeseries prediction task. This spin-VCSEL-based RC system shows a ten-fold improvement in processing speed, which can further be enhanced in a straightforward way by increasing the birefringence of the VCSEL chip.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Micro-Expression Recognition using 3D - CNN

2020 ◽  
pp. 5-13
Author(s):  
Vishal Dubey ◽  
◽  
◽  
◽  
Bhavya Takkar ◽  
...  
Keyword(s):  
Emotional Response ◽  
High Speed ◽  
Actual State ◽  
Time Interval ◽  
Short Time Interval ◽  
Expression Recognition ◽  
Specific Emotion ◽  
3D Cnn ◽  
Short Time ◽  
Micro Expression

Micro-expression comes under nonverbal communication, and for a matter of fact, it appears for minute fractions of a second. One cannot control micro-expression as it tells about our actual state emotionally, even if we try to hide or conceal our genuine emotions. As we know that micro-expressions are very rapid due to which it becomes challenging for any human being to detect it with bare eyes. This subtle-expression is spontaneous, and involuntary gives the emotional response. It happens when a person wants to conceal the specific emotion, but the brain is reacting appropriately to what that person is feeling then. Due to which the person displays their true feelings very briefly and later tries to make a false emotional response. Human emotions tend to last about 0.5 - 4.0 seconds, whereas micro-expression can last less than 1/2 of a second. On comparing micro-expression with regular facial expressions, it is found that for micro-expression, it is complicated to hide responses of a particular situation. Micro-expressions cannot be controlled because of the short time interval, but with a high-speed camera, we can capture one's expressions and replay them at a slow speed. Over the last ten years, researchers from all over the globe are researching automatic micro-expression recognition in the fields of computer science, security, psychology, and many more. The objective of this paper is to provide insight regarding micro-expression analysis using 3D CNN. A lot of datasets of micro-expression have been released in the last decade, we have performed this experiment on SMIC micro-expression dataset and compared the results after applying two different activation functions.

Plasma-Assisted Nitriding in Low-Frequency Inductively Coupled Plasma Enhanced with Ferromagnetic Cores

2018 ◽  
Vol 37 (6) ◽  
pp. 545-550
Author(s):  
Mikhail Isupov ◽  
Vadim Pinaev ◽  
Daria Mul ◽  
Natalia Belousova
Keyword(s):  
Inductively Coupled Plasma ◽  
High Speed ◽  
Low Frequency ◽  
Sample Surface ◽  
Ion Energy ◽  
Inductively Coupled ◽  
Steel Aisi ◽  
Current Densities ◽  
Aisi 321 ◽  
Stainless Steel Aisi

AbstractAn experimental investigation of plasma-assisted nitriding of austenitic stainless steel AISI 321 in a low-pressure (7 Pa), low-frequency (50–100 kHz) nitrogen inductively coupled plasma enhanced with ferromagnetic cores has been performed at the temperatures of 470–625 °C, sample biases of ‒500–‒750 V, current densities on the sample surface of 1.2–3.3 mA/cm2 and nitriding times of 20 and 60 min. It is found that even the short (20 min) ion-plasma treatment results in the formation of nitrided layers with the thickness of up to 40 μm and microhardness of up to 9 GPa.The high speed of nitriding can be explained as a result of the joint action of high ion flux density and high ion energy on the sample surface.

A new packaging technology using micro-solder bumps for high-speed photoreceivers

1992 ◽  
Vol 15 (4) ◽  
pp. 578-582 ◽  
Author(s):  
H. Tsunetsugu ◽  
K. Katsura ◽  
T. Hayashi ◽  
F. Ishitsuka ◽  
S. Hata
Keyword(s):  
High Speed ◽  
Packaging Technology ◽  
Solder Bumps
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