Metrology and Inspection for New Interconnects in Advanced Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001536-001552
Author(s):  
Russ Dudley ◽  
Matt Wilson ◽  
Rajiv Roy
Keyword(s):  
Surface Defects ◽  
High Volume ◽  
Electrical Performance ◽  
Sensor Technology ◽  
System Throughput ◽  
Wafer Level ◽  
Advanced Packaging ◽  
Equipment Utilization ◽  
Interferometric Sensor ◽  
3D Metrology

Interconnects for Advanced Packaging are getting smaller and come in a variety of sizes, shapes, and materials. The height, diameter, shape, and the absence/presence of these interconnects are critical and must be monitored across the device and wafer to ensure reliable connections during the bonding process. Solder bump technologies have been utilized in the past, but cannot support the high density interconnects that are required. New interconnect technologies being utilized for wafer level packaging (WLP) and through silicon via (TSV) packages include copper pillar posts and TSV posts. These new interconnect technologies provide higher density, improved reliability, and better electrical performance. This paper will highlight the critical metrology and inspection requirements for these new interconnect technologies and demonstrate the capability of a single platform to support these new interconnects for high volume manufacturing (HVM). The single platform includes 3D metrology performed using a proprietary interferometric sensor technology that can measure the height of the post and the thickness of the surrounding polymer at the same time to optimize the measurement performance and system throughput. The platform also provides the ability to inspect for surface defects, irregular posts, missing posts, and a variety of other inspections typically performed on bumped wafers or substrates. Both the metrology and inspection results from the single platform are output to a proprietary analysis package using industry standard Rudolph Result Files (RRF). The analysis will demonstrate the value these results provide for process control and the defect analysis, ultimately leading to improved yields and equipment utilization.

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

Automated Metrology Improves Productivity and Yields for Wafer Level Packaging in High Volume Manufacturing

2014 ◽  
Vol 2014 (1) ◽  
pp. 000155-000160
Author(s):  
Jin You Zao ◽  
Bong Yin Yen ◽  
Lim Beng Kuan ◽  
John Thornell ◽  
Darcy Hart ◽  
...  
Keyword(s):  
Process Control ◽  
High Volume ◽  
Critical Dimension ◽  
Thickness Measurement ◽  
Electrical Performance ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Under Sampling ◽  
Line Process ◽  
Increasing Demand

Wafer Bumping In-line Process control of Wafer-Level Chip Scale Package (WLCSP) requires accurate measurement of bump features during processing. These bump features include critical dimension of Redistribution Layer (RDL), Under Bump Metal (UBM) and transparent polyimide thickness. For a 4-Mask Layer Cu plated WLCSP, accurate feature thickness measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor. This paper reports the development of an automated Critical Dimension (CD) measurement solution capable of measuring features at pre-defined locations on different topology both under sampling and full inspection mode on wafer. The solution is fully scalable to meet the requirement of high product-mix HVM environment, by highly adaptive to different features on different products for which measurement needs to be automated for effective process control.

Wafer Thinning for Advanced Packaging Applications

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Scott Kroeger
Keyword(s):  
Low Cost ◽  
High Volume ◽  
Alternative Methods ◽  
Critical Element ◽  
Wafer Level ◽  
Temporary Bonding ◽  
Scale Down ◽  
Advanced Packaging ◽  
Wafer Thinning ◽  
Etch Profile

Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.

Current status and future prospects of panel level packaging

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000707-000750
Author(s):  
Santosh Kumar ◽  
Amandine Pizzagalli ◽  
Dave Towne ◽  
Thibault Buisson ◽  
Andrej Ivankovic ◽  
...  
Keyword(s):  
Semiconductor Industry ◽  
High Volume ◽  
Current Status ◽  
Flat Panel Display ◽  
Future Prospects ◽  
Wafer Level ◽  
Commercial Development ◽  
Economy Of Scale ◽  
Wafer Level Packaging ◽  
Advanced Packaging

Demand of lower cost with higher performances has driven the semiconductor industry to develop innovative solutions. One of the new approaches to reduce the overall cost is to switch from wafer to larger size panel format. The panel infrastructure has gained considerable interest from the semiconductor industry and is certainly a promising market due to its cost advantages and economy of scale benefits. Panel level manufacturing has the potential to leverage the knowledge and infrastructure of wafer level packaging as well as PCB / flat panel display / photovoltaic industries. We have identified six key packaging platforms which can be processed on larger surface (rectangular/square) such as FOWLP panel, organic interposer, glass panel interposer, hybrid interposer, embedded die as well as coreless substrate. Over the past years, it's become clear that some panel packages choices will be more suitable than others for successful commercial development. The equipment infrastructure within the advanced packaging supply chain today is mainly based on processing 300mm round wafers. However, to process larger surface, new equipment and optimized materials are required. The key question raised is when the panel industry will take off and how will it evolve? Are the supply chains ready to move to the panel scale manufacturing? What are the challenges / issues involved for the panel adoption to high volume manufacturing? This paper will try to answer these questions and discuss about the current status and future prospects of panel level packaging.

Challenges of Scalable 2.5D IC Assembly

2015 ◽  
Vol 12 (3) ◽  
pp. 123-128
Author(s):  
Liang Wang ◽  
Charles G. Woychik ◽  
Guilian Gao ◽  
Grant Villavicencio ◽  
Scott McGrath ◽  
...  
Keyword(s):  
High Volume ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
High Yield ◽  
Design Stage ◽  
Advantages And Disadvantages ◽  
Interconnect Delay ◽  
Temporary Bonding ◽  
Thermocompression Bonding ◽  
Advanced Packaging

Driven by key metrics, including higher computing performance, lower power consumption, smaller form factor, increased bandwidth, and reduced latency (interconnect delay), the semiconductor interconnect technology is transitioning to 2.5D and gaining acceptance in the industry, as an increasing number of products are beginning to enter volume manufacturing. To transition from today's low volumes to high volume manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput), and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process, and integration choices. With these concerns as a backdrop, our article will discuss our approach to optimizing 2.5D assembly for HVM. This article starts with a review of our test vehicle and our overall choices of substrate, interposer, and die dimensions. Three different 2.5D assembly approaches that have been investigated for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. It is our finding that for achieving high yield and reliability, in the design stage of the system detailed considerations must be given to not only the electrical performance and signal integrity but also the thermal and mechanical behavior of the system in operation as well as the entire process history. This article reports our results from critical areas including temporary bonding, thermocompression bonding, mass reflow, thin wafer/die handling, flux, underfill, and molding. This article also presents our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In the last portion of this article, recommendations are made for an optimized assembly process flow.

scholarly journals A Hermetic Advanced Packaging Solution for Optical Devices Using a Glass-Capping Technology on Wafer-Level

2009 ◽  
Vol 1 (1) ◽  
pp. 1527-1530
Author(s):  
S. Maus ◽  
U. Hansen ◽  
J. Leib ◽  
M. Töpper
Keyword(s):  
Optical Devices ◽  
Wafer Level ◽  
Advanced Packaging

Ultra-High-Density Interconnect Enabled by Hybrid Bonding for Heterogeneous Integration: Interfacial Characteristics

2021 ◽  
Author(s):  
Mei-Chien Lu
Keyword(s):  
Performance Metrics ◽  
High Volume ◽  
Image Sensor ◽  
Structure Design ◽  
High Density ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Bonding Area ◽  
The Impact ◽  
Interfacial Characteristics

Abstract Hybrid bonding has been explored for more than a decade and implemented recently in high volume production at wafer-to-wafer level for image sensor applications to enable high performance chip-stacking architectures with ultra-high-density chip-to-chip interconnect. The feasibility of sub-micron hybrid bond pitch leading to ultra-high-density chip-to-chip interconnect has been demonstrated due to the elimination of solder bridging issues from microbump method. Hybrid bonding has also been actively considered for logic and memory chip-stacking, chiplets, and heterogeneous integration in general but encountering additional challenges for bonding at die-to-wafer or die-to-die level. Overlay precision, throughput, wafer dicing are among the main causes. Widening the process margin against overlay error by designing innovative hybrid bonding pad structure is highly desirable. This work proposes a method to evaluate these hybrid bonding pad structure designs and to assess the potential performance metrics by analyzing interfacial characteristics at design phase. The bonding areas and ratios of copper-copper, copper-dielectric, and dielectric-dielectric are the proposed key parameters. The correlation between bonding area ratios and overlay errors can provide insights on the sensitivity to process margins. Nonetheless, the impact of copper recess or protrusion associated with bonding area ratios are also highlighted. The proposed method is demonstrated by examining and analyzing the hybrid bonding pad structure design concepts from a few cases reported in literatures as examples. Concerns are identified for elaboration in future designs and optimizations.

Development of High Density RDL Technologies for Panel Level Processing

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000284-000313
Author(s):  
Lars Böttcher ◽  
S. Karaszkiewicz ◽  
F. Schein ◽  
R. Kahle ◽  
A. Ostmann
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
High Density ◽  
Organic Films ◽  
High Yield ◽  
Wafer Level ◽  
Final Size ◽  
Process Yield ◽  
Cu Pillar ◽  
Thin Organic Films ◽  
Advanced Packaging

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.

Electrical Characterization on a High-Speed Wafer-Level Package

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  
Keyword(s):  
High Speed ◽  
Unit Length ◽  
Ground Plane ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Metal Loss ◽  
Signal Loss ◽  
Wafer Level ◽  
Wafer Level Package

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

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