Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

2018 ◽  
Vol 2018 (1) ◽  
pp. 000064-000068
Author(s):  
Amir Hanna ◽  
Arsalan Alam ◽  
G. Ezhilarasu ◽  
Subramanian S. Iyer

Abstract A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt <1μm, average die-shift of 3.28 μm with σ < 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000809-000825
Author(s):  
Bernard Adams ◽  
Won Kyung Choi ◽  
Duk Ju Na ◽  
Andy Yong ◽  
Seung Wook Yoon ◽  
...  

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.


2008 ◽  
Vol 1068 ◽  
Author(s):  
Augusto Gutierrez-Aitken ◽  
Patty Chang-Chien ◽  
Bert Oyama ◽  
Kelly Tornquist ◽  
Khanh Thai ◽  
...  

ABSTRACTTo meet increasingly challenging and complex systems requirements, it is not enough to use one single semiconductor technology but to integrate several high performance technologies in an efficient and cost effective way. Heterogeneous integration (HI) approaches lead to a significant higher design flexibility and performance. In this paper we present some of the HI approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology. More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the COSMOS DARPA program.


2021 ◽  
Author(s):  
Tc Chai ◽  
David Ho ◽  
Sc Chong ◽  
Ps Sharon Lim ◽  
Hy Hsiao ◽  
...  

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001847-001884
Author(s):  
Peter Ramm ◽  
Armin Klumpp ◽  
Alan Mathewson ◽  
Kafil M. Razeeb ◽  
Reinhard Pufall

The European 3D heterogeneous integration platform has been established by the consortium of the Integrated Project e-BRAINS [1], where technologies of the following relevant main categories of 3D integration are provided to enable future applications of smart sensor systems:3D System-on-Chip Integration - 3D-SOC: TSV technology for stacking of thinned devices or large IC blocks (global level),3D Wafer-Level-Packaging - 3D-WLP: embedding technology with through-polymer vias (TPV) for stacking of thinned ICs on wafer-level (no TSV), and3D System-in-Package - 3D-SIP: 3D stacking of packaged devices or substrates *definitions according to [2] Regarding TSV performance, the applications do not need ultra-high vertical interconnect densities as for 3D stacked Integrated Circuits – 3D-SIC*. Nevertheless, the lateral sizes of the TSVs are preferably minimized to allow for place and route for small “open” IC areas. Smaller TSVs are also preferred in order to reduce thermo-mechanical stress. e-BRAINS' focus is on how heterogeneous integration and sensor device technologies can be combined to bring new performance levels to targeted applications with high market potentials. The consortium, under coordination of Infineon and technical management by Fraunhofer EMFT, is composed of major European system manufacturers (Infineon, Siemens, SensoNor, 3D PLUS, Vermon and IQE), SMEs (DMCE, Magna Diagnostics, SORIN and eesy-ID), the large research institutions CEA Grenoble, Fraunhofer (EMFT Munich & IIS-EAS Dresden), imec, SINTEF, Tyndall and ITE Warsaw, and universities (EPFL Lausanne, TU Chemnitz and TU Graz). Target applications include automotive, ambient living and medical devices, with a specific focus on wireless sensor systems. Concerning the enabling 3D Heterogeneous Integration Platform, the e-BRAINS partners are working close together, where Infineon, Fraunhofer EMFT, imec and SINTEF are focusing mainly on 3D-SOC and 3D-WLP, and the French system manufacturer 3D PLUS and Tyndall on 3D-WLP and 3D-SIP technologies. The focus of this paper is on low-temperature bonding processes for highly reliable 3D integrated sensor systems. One of the key issues for heterogeneous systems production is the impact of 3D processes to the reliability of the product, i.e. the high built-in stresses caused by e.g. the CTE mismatch of complex layer structures (thin Si, ILDs, metals etc.) in combination with elevated bonding temperatures. As consequence, extensive project work was dedicated in the developments of reliable low-temperature bonding processes. Mainly intermetallic compound (IMC) bonding with Cu/Sn metal systems supported by ultrasonic agitation (Fraunhofer EMFT) was successfully introduced in 3D integration technology (see Fig. 2). A copper/tin solid-liquid interdiffusion (SLID) system was investigated using ultrasonic agitation to reduce the assembly temperature below the melting point of tin. Cleaning procedures are important shortly before joining the samples; dry cleaning has best results due to removal of thin oxide layers. Figure 2 shows a cross section of US supported Cu/Sn bonding at 150C. The intermetallic compounds Cu3Sn and Cu6Sn5 as well as pure tin easily can be identified. Due to low temperature assembly the most stable intermetallic compound (IMC) Cu3Sn has a minor share of the metal system. Most importantly there is no gap between top and bottom part of the joint despite the macroscopic assembly temperature is far away from the melting point of tin. But maybe the ultrasonic agitation brings enough energy to the interfaces, so locally melting can occur. In this way robust IMC bonding technology at 150C could be demonstrated with shear forces of 17 MPa and an alignment accuracy of 3 μm, well-suited for 3D integration. Figure 2: Low-temperature IMC bonding technology using ultrasonic agitation (Fraunhofer EMFT) Reliability for SLID contacts is certainly a very challenging objective especially looking for robust solutions in automotive applications. Thermally induced mechanical stress is the main reason for early fails during temperature cycling. Cross sectioned samples were investigated and methods like nanoindentation, Raman spectroscopy, fibDAC, and high local resolution x-ray scattering were applied to measure the intrinsic stresses. It can be shown that low temperature bonding is the right approach to avoid excessive stress cracking the interface or even fracturing the silicon. Also fatigue of metals can be reduced in a range that plastic deformation is no lifetime limiting factor.


Author(s):  
Maaike M. V. Taklo ◽  
Astrid-Sofie Vardøy ◽  
Ingrid De Wolf ◽  
Veerle Simons ◽  
H. J. van de Wiel ◽  
...  

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.


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