Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST

2008 ◽  
Vol 1068 ◽  
Author(s):  
Augusto Gutierrez-Aitken ◽  
Patty Chang-Chien ◽  
Bert Oyama ◽  
Kelly Tornquist ◽  
Khanh Thai ◽  
...  
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Heterogeneous Integration ◽  
Space Technology ◽  
Wafer Level ◽  
Selective Epitaxial Growth ◽  
Wafer Level Packaging ◽  
Design Flexibility ◽  
Systems Requirements ◽  
And Performance

ABSTRACTTo meet increasingly challenging and complex systems requirements, it is not enough to use one single semiconductor technology but to integrate several high performance technologies in an efficient and cost effective way. Heterogeneous integration (HI) approaches lead to a significant higher design flexibility and performance. In this paper we present some of the HI approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology. More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the COSMOS DARPA program.

Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

2018 ◽  
Vol 2018 (1) ◽  
pp. 000064-000068
Author(s):  
Amir Hanna ◽  
Arsalan Alam ◽  
G. Ezhilarasu ◽  
Subramanian S. Iyer
Keyword(s):  
High Performance ◽  
Metal Films ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Integration Platform ◽  
Wafer Level Packaging ◽  
Fine Pitch ◽  
Mechanical Bending

Abstract A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt <1μm, average die-shift of 3.28 μm with σ < 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.

Compliant Wafer Level Package

2001 ◽  
Author(s):  
Chirag Patel ◽  
Kevin P. Martin ◽  
James D. Meindl
Keyword(s):  
Performance Analysis ◽  
Integrated Circuits ◽  
High Performance ◽  
Wafer Level ◽  
Electronic Products ◽  
Packaging Technology ◽  
Technology Roadmap ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Wafer Level Package

Abstract A high I/O density and high performance wafer level packaging technology called the Compliant Wafer Level Package (CWLP) is reported. The necessity for compliant interconnects in upcoming generations of electronic products is discussed by analyzing the technology requirements projected by the International Technology Roadmap for Semiconductors (ITRS). To be a true wafer level package, the technology should have following three characteristics11: I) package all Integrated Circuits (ICs) intact on wafer at once, II) perform wafer level test and burn-in, and III) assemble the WLP on the system board without using an underfill. Compliant interconnects are essential to accomplishing wafer level test and assembly without underfill. These topics are discussed in the paper followed by fabrication and performance analysis of the CWLP technology.

Heterogeneous Integration on Fan-Out Wafer Level Packaging Platform

2021 ◽  
Author(s):  
Tc Chai ◽  
David Ho ◽  
Sc Chong ◽  
Ps Sharon Lim ◽  
Hy Hsiao ◽  
...  
Keyword(s):  
Heterogeneous Integration ◽  
Wafer Level ◽  
Wafer Level Packaging

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

Evaluation of Polymer Core Solderballs for Wafer Level Reliability Improvements

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000545-000566
Author(s):  
John Hunt ◽  
Adren Hsieh ◽  
Eddie Tsai ◽  
Chienfan Chen ◽  
Tsaiying Wang
Keyword(s):  
Temperature Cycling ◽  
Wafer Level ◽  
Development Activity ◽  
Wafer Level Packaging ◽  
First Case ◽  
Mask Design ◽  
To Come ◽  
And Performance ◽  
Reliability Performance ◽  
The Impact

Nearly half a century ago the first die bumping was developed by IBM that would later enable what we call Wafer Level Packaging. It took nearly 40 years for Wafer Level Chip Scale Packaging (WLCSP), with all of the “packaging” done while still in wafer form to come into volume production. It began with very small packages having solderball counts of 2–6 I/Os. Over the years, the I/O count has grown, but much of the industry perception has remained that WLCSPs are limited to low I/O count, low power applications. But within the last few years, there have been growing demands for WLCSP packages to expand into applications with higher levels of complexity. With the ever increasing density and performance requirements for components in mobile electronic systems, the need has developed for an expansion of applicability for Wafer Level Package (WLP) technology. Wafer Level packaging has demonstrated a higher level of component density and functionality than has been traditionally available using standard packaging. This has led to the development of WLCSPs with larger die and increasing solderball connectivity counts. Development activity has been ongoing for improved materials and structures to achieve the required reliability performance for these larger die. For this study, we have evaluated several different metallic structures used for polymer core solderballs with two different WLCSP structures. The WLCSP structures which were evaluated included a standard 4-mask design with redistribution layer (RDL), using a Polymer 1, Metal RDL, Polymer2, and Under Bump Metallization (UBM); as well as a 3-mask design with RDL, using a Polymer 1, Metal RDL, and Polymer 2. In the first case, the solderballs are bonded to the UBM, while in the second case the balls are bonded to the RDL, using the Polymer 2 layer as the solder wettable defining layer. All of the combinations are tested using the standard JEDEC Temperature Cycling on Board (TCOB) and Drop Test (DT) methodologies. The two different metallurgies of the polymer core solderballs appear to react differently to the two different WLCSP structures. This suggests that the polymer core solderball compositions may perform best when optimized for the specific WLCSP structures that are manufactured. We will review the results of the impact of the different polymer core metallurgies on the TCOB and DT reliability performance of the WLCSPs, showing the interactions of these materials with the two WLCSP structures.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Sign in / Sign up

Export Citation Format

Share Document