Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology

2011 ◽  
Vol 2011 (1) ◽  
pp. 000673-000682 ◽  
Author(s):  
Jonathan Tamil ◽  
Siew Hoon Ore ◽  
Kian Yeow Gan ◽  
Yang Yong Bo ◽  
Geraldine Ng ◽  
...  
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Flow Simulation ◽  
Experimental Tests ◽  
Initial Step ◽  
Design Parameters ◽  
Molding Process ◽  
Chip Technology ◽  
Molding Flow ◽  
Mold Flow

Increasing challenges are faced to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial Moldable Underfill (MUF) is used and in particular, during panel level molding. One key challenge faced is severe void entrapment under the die. Experiments involving a large DOE matrix, which require significant time and process resources, are typically used to solve this issue. 3D flow simulation can be used to optimize the process to reduce defects without doing actual runs. Mold flow simulation can effectively reduce the design-to-implementation cycle time, identifying key problems before actual fabrication. In this paper, 3D mold flow simulation using Moldex3DTM V10 is applied to transfer molding to optimize design and process parameters. This paper proposes and verifies a systematic method that can save computational resources by using 2 steps analysis: simplified panel simulation and single package simulation. The initial step, simplified panel level simulation, is to optimize the process parameters to obtain balanced melt front. The second step is to study on the package level the effect of various package-scale parameters. This analysis provides a prediction of the void location and an insight on the appropriate parameters to minimize void problem. The actual voids location and size from the experiment was captured by SAT machine and short shots were obtained. For final validation, a complete panel-level flow model is built, where the process and design parameters adopted in the actual molding were implemented. The mold filling simulation showed good correlation with the experimental short shots and actual void location. With optimized parameters from the simulation used as guidelines, experimental tests were conducted and the study showed that the simulation is a useful tool to optimize the molding process.

Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology

2012 ◽  
Vol 9 (1) ◽  
pp. 19-30 ◽  
Author(s):  
Jonathan Tamil ◽  
Siew Hoon Ore ◽  
Kian Yeow Gan ◽  
Drake Koh ◽  
Michael Gantalao Ti In ◽  
...  
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Flow Simulation ◽  
Design Parameters ◽  
Process Window ◽  
Process Data ◽  
3D Flow ◽  
Molding Process ◽  
Chip Technology ◽  
Mold Flow

Moldability is a crucial aspect of flip chip technology. It is an increasing challenge to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial molded underfill (MUF) is used and, in particular, during panel level molding. One key challenge faced is severe void entrapment beneath the die. Typically, large DOE matrix experiments are used to address this issue, which require significant time and process resources. 3D flow simulation can be used to optimize the process to reduce defects with a smaller number of actual runs. By correlating theoretical and experimental phenomena, flow simulation enhances the understanding of the complex fluid dynamics during the molding process. 3D flow simulation can assist in widening the process window, which is limited by the inherent machine and material challenges. This can be achieved by prediction of the effect of varying design, material, and process parameters on melt front behavior and void locations. 3D mold flow simulation using Moldex3D V10 is used to optimize the MUF transfer molding on selected flip chip devices. This paper proposes and verifies a systematic flow simulation methodology designed to save computational resources by using a three step analysis. The initial step, simplified panel level simulation, is to optimize the process parameters to obtain a balanced melt front. Next, on the package level, we studied the effect of various parameters. This analysis provides a prediction of the void location and an insight into the appropriate parameters to minimize the void problem. The optimized parameters from the preliminary simulation were used as guidelines. For the second step, a full validation was conducted. A complete full panel-level flow model was built, where the process and design parameters adopted in the actual molding were implemented. The actual void location and size from the experiment were captured by scanning acoustic microscope (SAM) machine and parallel lapping (p-lapping). Short shots were also obtained to study the melt front behavior. The panel mold filling simulations showed good correlation with the experimental short shots and actual void locations. The prediction capability is further enhanced by zooming in to the column level, and this enhanced model was able to predict the other lower risk voids away from the main problem areas. This was correlated with actual CSAM data and p-lapping. The 3D flow simulation enhances the understanding of causes of flow imbalance, void signature, void formation, and the effect of varying bump height, die thickness, mold cap thickness, gate height, die orientation, transfer profile, and mold temperature as potential enhancement measures. With a successful correlation between simulation and process data as shown in this paper, we have demonstrated that mold flow simulation is a reliable tool to effectively reduce the design-to-implementation cycle time, identifying potential key problems during actual fabrication and potential solutions to reduce defects.

Molding Recipe Study for MUF Solder Crack Improvement

2018 ◽  
Vol 2018 (1) ◽  
pp. 000121-000124
Author(s):  
Scott Chen ◽  
Leander Liang ◽  
Pallas Hsu ◽  
Tim Tsai ◽  
Mason Liang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Flow Simulation ◽  
Test Vehicle ◽  
Chip Technology ◽  
Solder Bumps ◽  
Capillary Underfill ◽  
Mold Flow ◽  
Profile Reduction ◽  
Transfer Pressure

Abstract In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

Advanced Simulation/Modeling and Reliability of Fine Pitch (130um) Lead-Free Flip-Chip Package

2008 ◽  
Author(s):  
Bahareh Banijamali ◽  
Ilyas Mohammed
Keyword(s):  
Fatigue Life ◽  
Life Prediction ◽  
Flip Chip ◽  
Solder Bump ◽  
Fatigue Life Prediction ◽  
Lead Free ◽  
Design Parameters ◽  
Chip Technology ◽  
Low K ◽  
Package Reliability

Flip-chip technology has been introduced in recent years which accommodate the ever increasing demands for higher performance and I/O density, while achieving smaller form factor and offering a cost effective solution. As the industry moves toward the 65nm and 45nm technology node, die sizes require a significant reduction while accommodating the need for tighter and finer pitches. For decades, the C4 process has served as the main interconnect method in the flip-chip package. But with bump pitches shrinking, the solder bump based C4 process is facing challenges in terms of reducing pitch and underfill process. At the same time, increasing challenges for flip-chip are seen by the movement toward lead-free solder bumps and low-k dielectric layers. This work conducted simulations and analyses on Tessera developmental μPILR flip chip package incorporating a 130um pitch bump array, using 3-D finite element method (FEM). This study explores the effect of various design parameters on package reliability while providing suggestions for selecting packaging materials. Based on modeling data certain set of over mold, underfill and thermal interface materials enhance overall package reliability performance. Solder fatigue life prediction was performed and solder bump reliability was compared for Tessera flip chip technology and standard flip chip solder joints using Modified Anand solder material properties and Darveaux fatigue life prediction theory. Further more, fracture mechanics approach was applied, and energy release rates were obtained in order to check reliability of low-k dielectric layer, provided passive/low-k material selection. The data presented here provides a baseline for reliability/feasibility of Tessera developmental μPILR flip chip package design for 130um bump pitch. Experimental reliability data is not complete at this time but will be available and published soon.

Computer-Aided Design of a TSOP II LOC Package Using Taguchi’s Parameter Design Method to Optimize Mold-Flow Balance

2003 ◽  
Vol 125 (2) ◽  
pp. 268-275 ◽  
Author(s):  
Hung-Lung Lee ◽  
Shyang-Jye Chang ◽  
Sheng-Jye Hwang ◽  
Francis Su ◽  
S. K. Chen
Keyword(s):  
Computer Aided Design ◽  
Design Method ◽  
Flow Simulation ◽  
Design Parameters ◽  
Packaging Design ◽  
Control Factors ◽  
Flow Balance ◽  
Robust Design Method ◽  
Aided Design ◽  
Mold Flow

This paper presents a methodology for TSOP II LOC packaging design. The design objectives are: 1) to optimize mold-flow balance, which in turn minimizes air traps, and 2) to minimize manufacturing variability, which implies optimal quality. A mold-flow simulation tool called C-MOLD is used to evaluate various design configurations. Taguchi’s robust design method is used for manufacturing variability considerations. The simulated results are verified with experimental flow patterns produced by means of “short shots.” In the nomenclature of the Taguchi method, mold-flow balance was chosen as quality characteristics and select a set of design parameters called control factors. The objectives are to find the levels of the control factors, which optimize the flow balance, and, at the same time, minimize the sensitivity of the variations of the control factors.

On-chip spiral inductor in flip-chip technology

2009 ◽  
Vol 1 (5) ◽  
pp. 431-440 ◽  
Author(s):  
Gye-An Lee ◽  
Darioush Agahi ◽  
Franco De Flaviis
Keyword(s):  
Flip Chip ◽  
Measurement Techniques ◽  
Silicon Layer ◽  
Design Parameters ◽  
Spiral Inductor ◽  
Back Side ◽  
Chip Technology ◽  
Return Path ◽  
On Chip ◽  
Current Return

Performance comparison is made between on-chip spiral inductor in flip-chip versus wirebond package technology. Full-wave electromagnetic simulation and on-strip measurement techniques were used to study the performance fluctuations of inductor within flip-chip environment. Results show that the performance of a flipped silicon-based spiral inductor is affected by the radio frequency (RF) current return path differences. The RF current return path for flip-chip is concentrated on the surface of silicon layer exclusively because back side ground under silicon is floating in flip-chip technology. In addition, the bump proximity effect is also considered. On-chip inductors in flip-chip environment must be optimized by reducing the eddy current in the silicon substrate and parasitic affects by adjusting design parameters. The equivalent circuit model of the flipped on-chip spiral inductor is verified with measured results over broadband frequencies. Also, the RF flip-chip characterization technique using on-strip measurement method is presented.

Optimization of Injection Molding Process Parameters to Increase the Tensile Strength in Polyamide-Specimen Using the Taguchi Method

2011 ◽  
Vol 341-342 ◽  
pp. 395-399 ◽  
Author(s):  
S. Esmail Mirvar ◽  
Ramin Mohamadi Kaleybar ◽  
Ahmad Afsari
Keyword(s):  
Mechanical Properties ◽  
Tensile Strength ◽  
Injection Molding ◽  
Process Parameters ◽  
Processing Parameters ◽  
Design Parameters ◽  
Injection Molding Process ◽  
Molding Process ◽  
Pressure Time ◽  
Injection Molded

Mechanical properties of plastic play an important role in defining the quality of injection molded products. Many studies have shown that mechanical properties of a product are influenced by the process parameters governing the injection-molding processes .This study employs Taguchi design parameters, to systematically investigate the influence of injection molding processing parameters on the tensile strength of Commercial grade Polyamide (PA-6). The result shows that the holding pressure time has main effect on the tensile strength, followed by cooling time, and holding pressure. Finally, a specimen produced according to the general form of the predictive equation of process parameters and verification test is performed on that. Test results show that the experimental value of tensile strength is very close to the estimated value.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

scholarly journals AC Current Ripple in Three-Phase Four-Leg PWM Converters with Neutral Line Inductor

Energies ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1430
Author(s):  
Aleksandr Viatkin ◽  
Riccardo Mandrioli ◽  
Manel Hammami ◽  
Mattia Ricco ◽  
Gabriele Grandi
Keyword(s):  
Numerical Simulations ◽  
Pulse Width Modulation ◽  
Neutral Line ◽  
Experimental Tests ◽  
Performance Comparison ◽  
Design Parameters ◽  
Switching Frequency ◽  
Three Phase ◽  
Ac Current ◽  
Current Ripple

This paper presents a comprehensive study of peak-to-peak and root-mean-square (RMS) values of AC current ripples with balanced and unbalanced fundamental currents in a generic case of three-phase four-leg converters with uncoupled AC interface inductors present in all three phases and in neutral. The AC current ripple characteristics were determined for both phase and neutral currents, considering the sinusoidal pulse-width modulation (SPWM) method. The derived expressions are simple, effective, and ready for accurate AC current ripple calculations in three- or four-leg converters. This is particularly handy in the converter design process, since there is no need for heavy numerical simulations to determine an optimal set of design parameters, such as switching frequency and line inductances, based on the grid code or load restrictions in terms of AC current ripple. Particular attention has been paid to the performance comparison between the conventional three-phase three-leg converter and its four-leg counterpart, with distinct line inductance values in the neutral wire. In addition to that, a design example was performed to demonstrate the power of the derived equations. Numerical simulations and extensive experimental tests were thoroughly verified the analytical developments.

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