scholarly journals Failure analysis and improvement of a non-metallic engineering part in an interference fit assembly process

2021 ◽  
Vol 0 (1) ◽  
pp. 2020002-0
Author(s):  
Kedong BI ◽  
◽  
◽  
Zhengming RUI ◽  
Lingchong XUE ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Assembly Process ◽  
Interference Fit

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

Frontside and Backside Analysis of Surface ESD

2008 ◽  
Author(s):  
Dermot Daly ◽  
Linda Grogan ◽  
Fergal Keating
Keyword(s):  
Failure Analysis ◽  
Cross Sections ◽  
Assembly Process ◽  
Front Side ◽  
Final Test ◽  
Strong Case ◽  
Encapsulation Process ◽  
Metal Filament ◽  
Static Discharge

Abstract In an effort to understand the failing mechanism of power to ground (Vdd-GND) shorts found on FPGA devices by standard ATE methods at Final Test; the recently discovered ESDFOS (Electro Static Discharge from Outside to Surface)[1] mechanism was revealed as the perpetrator. This ESDFOS was first brought to the attention of the authors when it was seen in the May 2005 issue of the EDFA magazine [2].The physical signatures of ESDFOS such as cracked SiN passivation, Al metal filament spiking, SiO2 dielectric break down can often be related to other failing mechanisms and it can therefore be difficult to irrefutably associate those physical signature to ESDFOS and to make a strong case for action. In this paper standard front side FIB cross sections combined with a novel backside technique were used to establish that the failing devices underwent an ESDFOS event prior to the epoxy encapsulation process. Using the failure analysis results alterations were made to the assembly process which have reduced the occurrence of Vdd-GND shorts.

Failure Analysis and Elimination of Galvanic Corrosion on Bondpads During Wafer Sawing

2000 ◽  
Author(s):  
Y. N. Hua ◽  
E. C. Low ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Failure Analysis ◽  
Feed Rate ◽  
Galvanic Corrosion ◽  
Experimental Results ◽  
Metal Corrosion ◽  
Wafer Fabrication ◽  
Al Alloy ◽  
Assembly Process ◽  
Water Problem ◽  
Sawing Process

Abstract In our previous paper [1], discolored bondpads due to galvanic corrosion were studied. The results showed that the galvanic corrosion occurred in 0.8 ìm wafer fabrication (fab) process with cold Al alloy (Al-Si, 0.8 wt%-Cu, 0.5 wt%) metallization. Galvanic corrosion is also known as a two-metal corrosion and it could be due to either wafer fab process or assembly process. Our initial suspicion was that it was due to a DI water problem during wafer sawing at assembly process. After that, we did further failure analysis and investigation work on galvanic corrosion of bondpads and further found that galvanic corrosion might be due to longer rinsing time of DI water during wafer sawing. The rinsing time of DI water is related to the cutting time of wafer sawing. Therefore, some experiments of wafer sawing process were done by using different sizes of wafer (1/8 of wafer, a quadrant of wafer and whole of wafer) and different sawing speed (feed-rate). The results showed that if the cutting time was longer than 25 minutes, galvanic corrosion occurred on bondpads. However, if the cutting time was shorter than 25 minutes, galvanic corrosion was eliminated. Based on the experimental results, it is concluded that in order to prevent galvanic corrosion of bondpads, it is necessary to select higher feed-rate during wafer sawing process at assembly houses. In this paper, we will report the details of failure analysis and simulation experimental results, including the solution to eliminate galvanic corrosion of bondpads during wafer sawing at assembly houses.

A Method to Enhance the Front-Side Lapping Process for Localisation of Sub-Surface Defect for Advanced Packages

2018 ◽  
Author(s):  
Sze Yee Tan ◽  
Chiu Soon Wong ◽  
Chea Wee Lo ◽  
Cin Sheng Goh
Keyword(s):  
Failure Analysis ◽  
Surface Defect ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Assembly Process ◽  
Front Side ◽  
Root Cause ◽  
The Common ◽  
Thinning Process ◽  
Non Destructive

Abstract In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.

Spin-On-Glass (SOG) Contamination Causing Single Via Failure

1997 ◽  
Author(s):  
P. Isakanian ◽  
S. Hunjan
Keyword(s):  
Failure Analysis ◽  
Local Area Networks ◽  
Local Area ◽  
Analysis Procedure ◽  
Assembly Process ◽  
Careful Observation ◽  
Failure Location ◽  
Lengthy Analysis

Abstract Several device failures were experienced after they went through the board assembly process. The failure caused severe transmit pulse attenuation from circuit block called AUI (Attachment Unit Interface). The AUI serves as a medium independent communication port in Local Area Networks. After careful observation and a series of Failure Analysis processes, the malfunction, which caused severe transmit pulse attenuation was attributed to a defective metal 1 to metal 2 via. The via in question is a tie between a pair of cascoded PMOS transistors in the analog section of the chip. These transistors serve as the main biasing leg for the AUI current sink. Since the via in question was bake recoverable at temperatures as low as 175°C for 20 minutes but would show the same failure signature when operated under temperature, the exact failure location was difficult to pinpoint. After a lengthy analysis procedure, the malfunction was attributed to contamination due to Spin On Glass (SOG) outgassing.

Failure Analysis of Redundant Escalator Chain Pin Retention Mechanisms

2011 ◽  
Author(s):  
Richard W. Klopp
Keyword(s):  
Failure Analysis ◽  
Driving Force ◽  
Lateral Force ◽  
Ring Groove ◽  
Side Plate ◽  
Interference Fit ◽  
Light Interference ◽  
Retaining Ring ◽  
Walking Mechanism ◽  
Rotation Sequence

The pins in new escalator chains were observed to have drifted laterally out of the chain side plates within a few hours of startup. The force driving this movement was sufficient to overcome a light interference fit and retaining rings intended to restrain the pins. Neither pins with heavy interference fit nor connector pins with sliding fits exhibited this tendency to drift. A failure analysis showed that even if the pins and side plates had been manufactured with a heavy interference fit, the sharp edge of the retaining ring groove acted as a broaching tool during assembly, shaving out and enlarging the side plate hole, and destroying the intended fit. The driving force for pin drift was traced to the hysteretic force and rotation sequence as the chain traveled around the escalator sprockets, which led to a walking mechanism that imparted a lateral force sufficient to move the pins and overcome the retaining rings.

Failure Mechanism Studies and Root Cause Identification of Nonstick on Pad on Microchip Al Bondpads

2014 ◽  
Author(s):  
Hua Younan ◽  
Zhou Yongkai ◽  
Chen Yixin ◽  
Fu Chao ◽  
Li Xiaomin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Wafer Fabrication ◽  
Assembly Process ◽  
Root Cause ◽  
Barrier Metal ◽  
Root Cause Identification ◽  
Induced Defects

Abstract It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.

Interference Fit Assembly of Micro-Parts Based on Microscopic Vision and Force

2015 ◽  
Vol 645-646 ◽  
pp. 1016-1023 ◽  
Author(s):  
Juan Zhang ◽  
Wen Rong Wu ◽  
Fei Shen ◽  
Yong Jun Deng
Keyword(s):  
Contact Force ◽  
Control Strategy ◽  
Interaction Force ◽  
Alignment Error ◽  
Assembly Process ◽  
Interference Fit ◽  
Micro Parts ◽  
Pose Alignment ◽  
Contact Position ◽  
Interference Fit Process

To assemble easily damaged micro-parts safely in interference fit way, the assembly process is designed and the interaction force in assembly process is analyzed. The pose of micro-parts is aligned based on calibration of three microscopic vision systems from different directions. In addition, a control strategy based on feedback of vision and force is proposed to assemble safely. In the case of two micro-parts just contact, position of micro-part is adjusted based on force information to compensate pose alignment error and keep force in safe range. When micro-part is deformed as increased contact force, position of micro-part is adjusted based on force in the interference fit process and deformation of micro-part. Experimental results demonstrate the effectiveness of proposed methods.

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