A numerical failure analysis on lead breakage issues of ultra fine pitch flip chip-on-flex and tape carrier packages during chip/film assembly process

2006 ◽  
Vol 46 (2-4) ◽  
pp. 487-495 ◽  
Author(s):  
Changsoo Jang ◽  
Seongyoung Han ◽  
Hangyu Kim ◽  
Sayoon Kang
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Assembly Process ◽  
Fine Pitch ◽  
Film Assembly

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill

2010 ◽  
Vol 2010 (1) ◽  
pp. 000798-000805 ◽  
Author(s):  
Sangil Lee ◽  
Daniel F. Baldwin
Keyword(s):  
Flip Chip ◽  
Void Nucleation ◽  
Void Formation ◽  
Bubble Nucleation ◽  
Nucleation Theory ◽  
High Yield ◽  
Process Conditions ◽  
Assembly Process ◽  
Fine Pitch ◽  
Underfill Material

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield. In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7% ) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively. This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results.

Corrections to "Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process"

2007 ◽  
Vol 30 (2) ◽  
pp. 359-359
Author(s):  
Robert W. Kay ◽  
Stoyan Stoyanov ◽  
Greg P. Glinski ◽  
Chris Bailey ◽  
Marc P. Y. Desmulliez
Keyword(s):  
Low Temperature ◽  
Flip Chip ◽  
Low Cost ◽  
Assembly Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Flip Chip Assembly

Influence of the Property of the Build-Up Package on Warpage at Flip Chip Assembly Process

2003 ◽  
Author(s):  
Yukihiko Toyoda ◽  
Yoichiro Kawamura ◽  
Hiroyoshi Hiei ◽  
Qiang Yu ◽  
Tadahiro Shibutani ◽  
...  
Keyword(s):  
Flip Chip ◽  
Electronic Device ◽  
New Product ◽  
High Density ◽  
Simulation Technique ◽  
Assembly Process ◽  
Reliability Problem ◽  
Fine Pitch ◽  
Flip Chip Assembly ◽  
Single Material

High density and integrated packaging of electronic device requires fine pitch. This packaging causes reliability problem in electronic device. One of them, warpage of the package occurred at chip assembly process may affect reliability. Therefore, if the simulation at the time of a chip assembly process is possible, it will be able to evaluate warpage in advance. It is very effective for development of a new product. Then, in this paper, the build-up package is regarded as a single material and the simulation technique of accuracy warpage at the time of chip assembly is reported. Next it is investigated the simulation technique for package warpage at the chip assembly process. Finnaly, it analyzed about the properties which affect warpage.

Ultra-Fine Pitch Stencil Printing for a Low Cost and Low Temperature Flip-Chip Assembly Process

2007 ◽  
Vol 30 (1) ◽  
pp. 129-136 ◽  
Author(s):  
Robert W. Kay ◽  
Stephen Stoyanov ◽  
Greg P. Glinski ◽  
Chris Bailey ◽  
Marc P. Y. Desmulliez
Keyword(s):  
Low Temperature ◽  
Flip Chip ◽  
Low Cost ◽  
Assembly Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Flip Chip Assembly

Simulation and Experiment of Molded Underfill Voids

2012 ◽  
Vol 2012 (1) ◽  
pp. 000359-000365 ◽  
Author(s):  
MyoungSu Chae ◽  
Eric Ouyang ◽  
JaeHan Chung ◽  
DokOk Yu ◽  
SeonMo Gu ◽  
...  
Keyword(s):  
Numerical Simulation ◽  
Flip Chip ◽  
Early Stage ◽  
Assembly Process ◽  
Molding Compound ◽  
Fine Pitch ◽  
Simulation And Experiment ◽  
Computational Resources ◽  
The Cost ◽  
Fem Numerical Simulation

The molded underfill (MUF) has become one of the trends in the IC packaging industry due to its simplification of assembly process steps and the saving of the cost. However, for the fine pitch flip chip bumping array, the void generation is one serious issue causing the short of the electrical connections and the cracking of the bumps. In this paper, the main focus is to predict the void generation and to compare with the experimental data. The early stage FEM numerical simulation not only can predict the risk of voids but also provide the best economic approach without the need to spend trial and error budget. A multiple segments substrate strip, with totally 64 packages populated on it, is used in the experiment. The manufacturing process parameters are programmed and recorded for comparison. The filling, packing, and curing of molding compound are carefully chosen in order to compare their effects. After the assembly process, each package is scanned with C-SAM inspection to check if the voids appear. For FEM numerical simulation, only one segment of the substrate strip, with totally 16 packages, is modeled to save computational resources and time. However, all the bumps, on each of the package, are modeled in order to check how the flow field is affected by the packages. In conclusion, we have obtained good match of experimental vs. simulation data. The prediction of voiding location is very close to each other.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

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