scholarly journals Simulation Study of the Use of AlGaN/GaN Ultra-Thin-Barrier HEMTs with Hybrid Gates for Achieving a Wide Threshold Voltage Modulation Range

Materials ◽  
2022 ◽  
Vol 15 (2) ◽  
pp. 654
Author(s):  
Shouyi Wang ◽  
Qi Zhou ◽  
Kuangli Chen ◽  
Pengxiang Bai ◽  
Jinghai Wang ◽  
...  
Keyword(s):  
Hole Concentration ◽  
Drain Current ◽  
Device Performance ◽  
Depletion Effect ◽  
Threshold Voltages ◽  
Gate Structure ◽  
Drain Side ◽  
Effective Reduction ◽  
Field Peak ◽  
Thin Barrier

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (VTH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect assisted by the p-GaN gate part, the VTH of HG-UTB HEMTs can be significantly increased. By tailoring the hole concentration of the p-GaN gate, the VTH can be flexibly modulated from 1.63 V to 3.84 V. Moreover, the MIS-gate part enables the effective reduction in the electric field (E-field) peak at the drain-side edge of the p-GaN gate, which reduces the potential gate degradation originating from the high E-field in the p-GaN gate. Meanwhile, the HG-UTB HEMTs exhibit a maximum drain current as high as 701 mA/mm and correspond to an on-resistance of 10.1 Ω mm and a breakdown voltage of 610 V. The proposed HG-UTB HEMTs are a potential means to achieve normally off GaN HEMTs with a promising device performance and featuring a flexible VTH modulation range, which is of great interest for versatile power applications.

scholarly journals High Performance Enhancement-Mode AlGaN/GaN MIS-HEMT with Selective Fluorine Treatment

2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Chao Yang ◽  
Jiayun Xiong ◽  
Jie Wei ◽  
Junfeng Wu ◽  
Bo Zhang ◽  
...  
Keyword(s):  
High Performance ◽  
Performance Enhancement ◽  
Drain Current ◽  
Depletion Region ◽  
Passivation Layer ◽  
Mis Structure ◽  
Enhancement Mode ◽  
Depletion Effect ◽  
Field Peak ◽  
Channel Region

A novel enhancement-mode (E-mode) Metal-Insulator-Semiconductor- (MIS-) HEMT with selective fluorine ion (F−) treatment is proposed and its mechanism is investigated. The HEMT features the Selective F−treatment both in the AlGaN channel region and in the thick passivation layer between the gate and drain (SFCP-MIS-HEMT). First, the F−in the passivation layer not only extends the depletion region and thus enhances the average electric field (E-field) between the gate and drain by the assisted depletion effect but also reduces theE-field peak at the gate end, leading to a higher breakdown voltage (BV). Second, in the AlGaN channel region, the F−region realizes the E-mode and the region without F−maintains a high drain current (ID). Third, MIS structure suppresses the gate leakage current, increasing the gate swing voltage and the BV. Compared with a MIS-HEMT with F−treatment in whole channel (FC-MIS-HEMT), SFCP-MIS-HEMT increases the BV by 46% and the saturation drain current (ID,sat) by 28%.

Fabrication of 700V SiC-SIT with Ultra-Low On-Resistance of 1.01mΩ•cm2

2006 ◽  
Vol 527-529 ◽  
pp. 1219-1222 ◽  
Author(s):  
Yasunori Tanaka ◽  
Koji Yano ◽  
Mitsuo Okamoto ◽  
Akio Takatsuka ◽  
Kenji Fukuda ◽  
...  
Keyword(s):  
Drain Current ◽  
Wide Bandgap ◽  
Device Performance ◽  
Power Switching ◽  
Static Induction Transistors ◽  
Gate Structure ◽  
Class Power ◽  
Trench Structure ◽  
Wide Bandgap Materials ◽  
Gate Region

Silicon carbide static induction transistors with submicron buried p+ gate (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicron buried p+ gate structure was fabricated by the combination of submicron trench dry etching and epitaxial growth process on a trench structure. As the device performance is mainly determined by the width of the p+ gate region and the spacing between two adjacent p+ gate regions, corresponding to the width of n- channel, we have optimized these parameters carefully using a device simulator. The breakdown voltage VBR and specific on-resistance RonS of the fabricated BGSIT were 700 V at a gate voltage VG = –12 V and 1.01 m/·cm2 at VG = 2.5 V and a drain current density JD = 200 A/cm2, respectively. This RonS is the lowest on-resistance for ~ 600V class power switching devices, including other wide-bandgap materials such as GaN.

Evaluation of Degradation due to Electron Irradiation of Si1-xCx S/D n-type MOSFETs

2014 ◽  
Vol 778-780 ◽  
pp. 1197-1200
Author(s):  
Masato Hori ◽  
Yuki Asai ◽  
Masashi Yoneoka ◽  
Isao Tsunoda ◽  
Kenichiro Takakura ◽  
...  
Keyword(s):  
Electron Irradiation ◽  
Electron Mobility ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Enhancement Effect ◽  
Device Performance ◽  
Irradiation Effects ◽  
Radiation Induced ◽  
Improve Device

To solve the problem of the limitation to improve device performance in standard Si integration technologies and to develop radiation-harsh devices, the irradiation effects of Si1-xCx source/drain (S/D) n-type metal oxide semiconductor field effect transistors (n-MOSFETs) have been investigated. It is shown that the drain current and the maximum electron mobility of Si1-xCx n-MOSFETs decrease by electron irradiation. The reduction of the device performance can be explained by the radiation-induced lattice defects in the devices. However, the electron mobility enhancement effect by adding C remained after an electron irradiation up to 5×1017 e/cm2.

Recessed gate GaN MESFETs fabricated by the photoelectrochemical etching process

1999 ◽  
Vol 572 ◽  
Author(s):  
Won Sang Lee ◽  
Yoon Ho Choi ◽  
Ki Woong Chung ◽  
Moo Whan Shin ◽  
Dong Chan Moon
Keyword(s):  
Electrochemical Etching ◽  
Etching Rate ◽  
Drain Current ◽  
Etching Process ◽  
Device Performance ◽  
High Activation ◽  
Band Bending ◽  
Photoelectrochemical Etching ◽  
Characteristic Frequencies ◽  
Recessed Gate

ABSTRACTA new photo-electrochemical etching method was developed and used to fabricate GaN MESFETs. The etching process uses photoresist for masking illumination and the etchant is KOH based. The etching rate with 1.0 mol% of KOH for n-GaN is as high as 1600 Å/min under the Hg illumination of 35 mW/cm/2. The MESFET saturates at VDS = 4 V and pinches off at VGS = −3 V. The maximum drain current of the device is 230 mA/mmn at 300 K and the value is remained almost same for 500 K operation. The characteristic frequencies, fT and fmax, are 6.35 GHz and 10.25 GHz, respectively. Insensitivity of the device performance to temperature was attributed to the defect-related high activation energy of dopants for ionization and band-bending at the subgrain boundaries in GaN thin films.

A Recessed-Gate In0.52Al0.48As/n+-In0.53Ga0.47As Misfet

1988 ◽  
Vol 144 ◽  
Author(s):  
Jesús A. del Alamo ◽  
Takashi Mizutani
Keyword(s):  
High Performance ◽  
Current Gain ◽  
Device Performance ◽  
Promising Candidate ◽  
Gate Structure ◽  
Source Resistance ◽  
Heavily Doped ◽  
Recessed Gate ◽  
Improve Device ◽  
A Current

ABSTRACTScaling of the In0.52Al0.48As insulator thickness of In0.52Al0.48As/n+-In0.53Ga0.47As MIStype FET's is experimentally found to result in a drastic drop of performance below 200 Å. This is demonstrated to arise from an increase in the sheet resistance of the extrinsic portions of the device that accompanies insulator scaling. In order to solve this problem, a recessed-gate dopedchannel MISFET with a very thin (300 Å) n+-In0.53Ga0.47As cap layer has been fabricated. A 1.5 μm long gate device showed a transconductance of 285 mS/mm and a current-gain cut-off frequency of 19.4 GHz. This result proves the ability of a thin n+-In0.53Ga0.47As cap to reduce source resistance and improve device performance. The fabricated recessed-gate structure is a promising candidate for high-performance scaled MIS-type FET's based on thin, heavily-doped In0.53Gav0.47 As channels.

scholarly journals Growth and Device Performance of AlGaN/GaN Heterostructure with AlSiC Precoverage on Silicon Substrate

2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
Jae-Hoon Lee ◽  
Jung-Hee Lee
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Film Growth ◽  
Drain Current ◽  
Device Performance ◽  
Wetting Layer ◽  
Si Substrate ◽  
Effect Transistor ◽  
Gan Heterostructure

A crack-free AlGaN/GaN heterostructure was grown on 4-inch Si (111) substrate with initial dot-like AlSiC precoverage layer. It is believed that introducing the AlSiC layer between AlN wetting layer and Si substrate is more effective in obtaining a compressively stressed film growth than conventional Al precoverage on Si surface. The metal semiconductor field effect transistor (MESFET), fabricated on the AlGaN/GaN heterostructure grown with the AlSiC layer, exhibited normally on characteristics, such as threshold voltage of −2.3 V, maximum drain current of 370 mA/mm, and transconductance of 124 mS/mm.

An Extensive Simulation Study of Gate Underlap Influence on Device Performance of Surrounding Gate In0.53Ga0.47As/InP Hetero Field Effect Transistor

2020 ◽  
Vol 10 (2) ◽  
pp. 157-165
Author(s):  
Soumya S. Mohanty ◽  
Urmila Bhanja ◽  
Guru P. Mishra
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Model Simulation ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Short Channel ◽  
Effect Transistor ◽  
Rf Performance ◽  
Gate Underlap

Background: This work describes the implementation of In0.53Ga0.47As/InP Surrounding Metal Gate Oxide Semiconductor Heterostructure Field Effect Transistor (SG MOSHFET) with gate underlap on both source and drain end to improve the DC and RF performance. Methods: A comprehensive and methodological investigation of DC and RF performance of III-V semiconductor are made for different underlap length varying from 5nm to 30nm on both sides of the device, which is used to mitigate the short channel issues to improve the device performance. Hydrodynamic model has been taken into consideration for the device simulation and it also includes Auger recombination and the Shockley–Read–Hall (SRH) model. Simulation is performed to analyze the various analog performance of device like drain current, surface potential, transconductance, threshold voltage, drain induced barrier lowering, off current, subthreshold slope, Ion/Ioff ratio, output conductance, intrinsic delay, energy-delay product, transconductance generation factor and radio frequency performance of device, like trans-frequency product and cut-off frequency. Results: From the simulation, it can be observed that an improved analog and RF performance is obtained at the optimum underlap length. Conclusion: This work delivers an idea for extended researchers to investigate different aspects of group III–V underlap MOSFETs.

The Dependence of Poly-Si TFT Characteristics on the Relative Misorientation Between Grain Boundaries and the Active Channel

2000 ◽  
Vol 621 ◽  
Author(s):  
Y.H. Jung ◽  
J.M. Yoon ◽  
M.S. Yang ◽  
W.K. Park ◽  
H.S. Soh ◽  
...  
Keyword(s):  
Grain Boundaries ◽  
Device Performance ◽  
Boundary Misorientation ◽  
Leakage Currents ◽  
Hot Carrier ◽  
Glass Substrates ◽  
Notable Effect ◽  
Threshold Voltages ◽  
Grain Boundary Misorientation ◽  
Active Channel

ABSTRACTWe present device-related experimental results that quantitatively reveal the effect of varying the active channel/grain-boundary misorientation on the resulting TFT characteristics. Specifically, using low-temperature SLS processes, we have fabricated and analyzed n-channel and p-channel devices (40 μm width × 8 μm length) with three different orientations of the channel with respect to the grain boundaries: parallel, 45° inclined, and perpendicular on Corning 1737 glass substrates.The results reveal that the TFTs with the best (worst) characteristics were obtained for the devices with parallel (perpendicular) alignment. In general, for both n- and p-channel devices, the most prominent orientation-dependent effects were observed in the values of the field effect mobilities, which were 340, 227, and 141 cm2/Vsec for n-channel devices and 145, 105, and 80 cm2/Vsec for p-channel devices, in the order of increasing orientation mismatch. In contrast, no notable effect was manifested in the leakage currents, while small effects were seen for the sub-threshold slopes and threshold voltages. The degradation of device performance under hot-carrier stress was found to decrease with increasing orientation mismatch.

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