Comprehensive investigation on RF/analog parameters in ferroelectric tunnel FET

Author(s):  
Rajesh Saha ◽  
Rupam Goswami ◽  
Brinda Bhowmick ◽  
Srimanta Baishya

Abstract In this paper, the effect of ferroelectric layer thickness (tFE), coercive field (Ec), remnant polarization (Pr), and saturation polarization (Ps) on transfer characteristic is highlighted for a Ferroelectric Tunnel FET (Fe-TFET) through a commercial TCAD simulator. Further, we have reported the RF/analog parameters like transconductance (gm), output conductance (gd), gain (gm/gd), gate capacitance (Cgg), and cut off frequency (ft) for wide range of FE parameters in Fe-TFET. Improved RF/analog performance and transfer characteristic are obtained for low value of tFE, Pr, Ec, whereas, these behavior is degraded at high value of Ps.

2019 ◽  
Vol 694 ◽  
pp. 133565 ◽  
Author(s):  
Myrsini Papageorgiou ◽  
Ioannis Zioris ◽  
Theocharis Danis ◽  
Dimitrios Bikiaris ◽  
Dimitra Lambropoulou

1999 ◽  
Vol 602 ◽  
Author(s):  
Daniel Lundström ◽  
Jan Yilbar ◽  
S.I. Khartsev ◽  
Alex Grishin ◽  
Masanori Okuyama

AbstractEpitaxial ferroelectric/colossal magnetoresistive PbZr0.52Ti0.48O3/La0.7(Pb,Sr)0.3MnO3 (PZT/LPSMO) thin film heterostructures have been grown onto SrTiO3 single crystals by KrF pulsed laser deposition technique to fabricate nonvolatile magnetosensitive memory. Colossal magnetoresisitivity (CMR) in LPSMO film has been tailored to room temperature by compositional control to get the maximum temperature coefficient of resistivity of 7.3 %K−1 @ 295 K and maximim magnetoresistivity of 27% @ 7 kOe and 300 K. The main processing parameters have been optimized to preserve CMR performance in LPSMO film after deposition of the top ferroelectric layer. Vertical Au/PZT/LPSMO/STO capacitor cell possesses very high dielectric permittivity about 1500 and rather low loss of 5% at 1 kHz, saturation polarization of 40.4 µC/cm2, remnant polarization of 20.6 µC/cm2, coercive field of 22.8 kV/cm, and no visible fatigue after 1.33.108 reversals. Three top contact metals: Au, Pt, and Ta, deposited at room temperature, have been examined. As compared with Ta, Pt and Au top contacts show superior performance regarding to combined properties: high remnant and saturation polarization, low loss and no fatigue while top Ta contacts have been found to be more efficient to reduce leakage in ferroelectric film.


Author(s):  
Shunichi Sakuragi ◽  
Daisuke Torii

In recent years, in the cooling technology for high-power electronic devices such as power transistors used for drive motor control of electric vehicles and hybrid vehicles, a method of flowing a cooling fluid to a cooling substrate having a fin structure has become the main technology. The structure of the cooling fluid flow path is a channel flow through multiple narrow plate gaps to secure a heat transfer area. In this study, the heat transfer characteristics when the aspect ratio of the channel having a flat rectangular cross-section was changed were investigated in detail by experiments. Moreover, the difference in the heat transfer characteristic at the time of making a rectangular flow path into vertical installation and horizontal installation was also investigated.


2018 ◽  
Vol 13 (2) ◽  
pp. 1-7
Author(s):  
Rafael Assalti ◽  
Denis Flandre ◽  
Michelly De Souza

This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The influence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measurements. The transconductance, output conductance, Early voltage and intrinsic voltage gain have been used as figure of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been obtained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.


2022 ◽  
Author(s):  
Harshit Kansal ◽  
Aditya S Medury

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>


2007 ◽  
Vol 2 (2) ◽  
pp. 104-110
Author(s):  
Michelly De Souza ◽  
Marcelo A. Pavanello

This paper presents charge-based continuous equations for the transconductance and output conductance of submicrometer Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. The effects of carrier velocity saturation, channel length modulation and drain-induced barrier lowering were taken into account in the proposed equations. Experimental results were used to test the validity of the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement in a wide range of bias.


2022 ◽  
Author(s):  
Hongling Yan ◽  
Yinlin Zhou ◽  
Fei Tang ◽  
Chengjiu Wang ◽  
Jing Wu ◽  
...  

Ligusticum chuanxiong Hort. (CX) is a medicinal and edible plant with a wide range of constituents of biological interest. Since the biomass of the non-medicinal parts of CX is huge,...


Sign in / Sign up

Export Citation Format

Share Document